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target/riscv: Expose interrupt pending bits as GPIO lines

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Expose the 12 interrupt pending bits in MIP as GPIO lines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-08-30 15:34:20 +10:00
parent 15732b8ed2
commit 0f0b70eeec
1 changed files with 30 additions and 0 deletions
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30
target/riscv/cpu.c
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@ -567,11 +567,41 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
mcc->parent_realize(dev, errp); mcc->parent_realize(dev, errp);
} }
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_set_irq(void *opaque, int irq, int level)
{
RISCVCPU *cpu = RISCV_CPU(opaque);
switch (irq) {
case IRQ_U_SOFT:
case IRQ_S_SOFT:
case IRQ_VS_SOFT:
case IRQ_M_SOFT:
case IRQ_U_TIMER:
case IRQ_S_TIMER:
case IRQ_VS_TIMER:
case IRQ_M_TIMER:
case IRQ_U_EXT:
case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
break;
default:
g_assert_not_reached();
}
}
#endif /* CONFIG_USER_ONLY */
static void riscv_cpu_init(Object *obj) static void riscv_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
cpu_set_cpustate_pointers(cpu); cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
#endif /* CONFIG_USER_ONLY */
} }
static Property riscv_cpu_properties[] = { static Property riscv_cpu_properties[] = {