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Less hardcoding of TARGET_USER_ONLY.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2008-07-23 16:14:22 +00:00
parent 477e3edf8b
commit 0eaef5aa01
6 changed files with 290 additions and 393 deletions
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95
target-mips/op_helper.c
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@ -596,59 +596,7 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
}
#endif /* TARGET_MIPS64 */
#ifdef CONFIG_USER_ONLY
void do_mfc0_random (void)
{
cpu_abort(env, "mfc0 random\n");
}
void do_mfc0_count (void)
{
cpu_abort(env, "mfc0 count\n");
}
void cpu_mips_store_count(CPUState *env, uint32_t value)
{
cpu_abort(env, "mtc0 count\n");
}
void cpu_mips_store_compare(CPUState *env, uint32_t value)
{
cpu_abort(env, "mtc0 compare\n");
}
void cpu_mips_start_count(CPUState *env)
{
cpu_abort(env, "start count\n");
}
void cpu_mips_stop_count(CPUState *env)
{
cpu_abort(env, "stop count\n");
}
void cpu_mips_update_irq(CPUState *env)
{
cpu_abort(env, "mtc0 status / mtc0 cause\n");
}
void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
cpu_abort(env, "mtc0 status debug\n");
}
void do_mtc0_status_irqraise_debug (void)
{
cpu_abort(env, "mtc0 status irqraise debug\n");
}
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
cpu_abort(env, "mips_tlb_flush\n");
}
#else
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
target_ulong do_mfc0_mvpcontrol (void)
{
@ -1582,44 +1530,6 @@ target_ulong do_yield(target_ulong t0)
return env->CP0_YQMask;
}
/* CP1 functions */
void fpu_handle_exception(void)
{
#ifdef CONFIG_SOFTFLOAT
int flags = get_float_exception_flags(&env->fpu->fp_status);
unsigned int cpuflags = 0, enable, cause = 0;
enable = GET_FP_ENABLE(env->fpu->fcr31);
/* determine current flags */
if (flags & float_flag_invalid) {
cpuflags |= FP_INVALID;
cause |= FP_INVALID & enable;
}
if (flags & float_flag_divbyzero) {
cpuflags |= FP_DIV0;
cause |= FP_DIV0 & enable;
}
if (flags & float_flag_overflow) {
cpuflags |= FP_OVERFLOW;
cause |= FP_OVERFLOW & enable;
}
if (flags & float_flag_underflow) {
cpuflags |= FP_UNDERFLOW;
cause |= FP_UNDERFLOW & enable;
}
if (flags & float_flag_inexact) {
cpuflags |= FP_INEXACT;
cause |= FP_INEXACT & enable;
}
SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
SET_FP_CAUSE(env->fpu->fcr31, cause);
#else
SET_FP_FLAGS(env->fpu->fcr31, 0);
SET_FP_CAUSE(env->fpu->fcr31, 0);
#endif
}
#ifndef CONFIG_USER_ONLY
/* TLB management */
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
@ -1743,8 +1653,6 @@ void r4k_do_tlbr (void)
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
#endif /* !CONFIG_USER_ONLY */
/* Specials */
target_ulong do_di (void)
{
@ -1821,6 +1729,7 @@ void do_deret (void)
debug_post_eret();
env->CP0_LLAddr = 1;
}
#endif /* !CONFIG_USER_ONLY */
target_ulong do_rdhwr_cpunum(void)
{