mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-12-11 16:00:50 -07:00
Less hardcoding of TARGET_USER_ONLY.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
477e3edf8b
commit
0eaef5aa01
6 changed files with 290 additions and 393 deletions
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@ -206,26 +206,23 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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return ret;
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}
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#if defined(CONFIG_USER_ONLY)
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#else
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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target_ulong phys_addr;
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int prot;
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if (env->user_mode_only)
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return addr;
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else {
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target_ulong phys_addr;
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int prot;
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
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return -1;
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return phys_addr;
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
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return -1;
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return phys_addr;
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}
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}
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void cpu_mips_init_mmu (CPUState *env)
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{
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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@ -318,7 +315,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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return ret;
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}
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#if !defined(CONFIG_USER_ONLY)
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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@ -354,232 +350,230 @@ static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_C2E] = "precise coprocessor 2",
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[EXCP_CACHE] = "cache error",
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};
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#endif
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void do_interrupt (CPUState *env)
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{
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#if !defined(CONFIG_USER_ONLY)
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target_ulong offset;
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int cause = -1;
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const char *name;
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if (!env->user_mode_only) {
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target_ulong offset;
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int cause = -1;
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const char *name;
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
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name = "unknown";
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else
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name = excp_names[env->exception_index];
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
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name = "unknown";
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else
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name = excp_names[env->exception_index];
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fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
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__func__, env->active_tc.PC, env->CP0_EPC, name);
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}
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if (env->exception_index == EXCP_EXT_INTERRUPT &&
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(env->hflags & MIPS_HFLAG_DM))
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env->exception_index = EXCP_DINT;
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offset = 0x180;
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switch (env->exception_index) {
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case EXCP_DSS:
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env->CP0_Debug |= 1 << CP0DB_DSS;
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/* Debug single step cannot be raised inside a delay slot and
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* resume will always occur on the next instruction
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* (but we assume the pc has always been updated during
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* code translation).
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*/
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env->CP0_DEPC = env->active_tc.PC;
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goto enter_debug_mode;
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case EXCP_DINT:
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env->CP0_Debug |= 1 << CP0DB_DINT;
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goto set_DEPC;
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case EXCP_DIB:
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env->CP0_Debug |= 1 << CP0DB_DIB;
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goto set_DEPC;
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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goto set_DEPC;
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_DEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
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__func__, env->active_tc.PC, env->CP0_EPC, name);
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}
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if (env->exception_index == EXCP_EXT_INTERRUPT &&
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(env->hflags & MIPS_HFLAG_DM))
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env->exception_index = EXCP_DINT;
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offset = 0x180;
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switch (env->exception_index) {
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case EXCP_DSS:
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env->CP0_Debug |= 1 << CP0DB_DSS;
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/* Debug single step cannot be raised inside a delay slot and
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resume will always occur on the next instruction
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(but we assume the pc has always been updated during
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code translation). */
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env->CP0_DEPC = env->active_tc.PC;
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}
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00480;
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break;
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case EXCP_RESET:
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cpu_reset(env);
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break;
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case EXCP_SRESET:
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env->CP0_Status |= (1 << CP0St_SR);
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memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
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goto set_error_EPC;
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case EXCP_NMI:
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env->CP0_Status |= (1 << CP0St_NMI);
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set_error_EPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_ErrorEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_ErrorEPC = env->active_tc.PC;
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}
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00000;
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break;
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case EXCP_EXT_INTERRUPT:
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cause = 0;
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if (env->CP0_Cause & (1 << CP0Ca_IV))
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offset = 0x200;
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goto set_EPC;
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case EXCP_LTLBL:
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cause = 1;
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goto set_EPC;
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case EXCP_TLBL:
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cause = 2;
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
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#if defined(TARGET_MIPS64)
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int R = env->CP0_BadVAddr >> 62;
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
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offset = 0x080;
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else
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#endif
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offset = 0x000;
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}
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goto set_EPC;
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case EXCP_TLBS:
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cause = 3;
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
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#if defined(TARGET_MIPS64)
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int R = env->CP0_BadVAddr >> 62;
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
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offset = 0x080;
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else
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#endif
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offset = 0x000;
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}
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goto set_EPC;
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case EXCP_AdEL:
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cause = 4;
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goto set_EPC;
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case EXCP_AdES:
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cause = 5;
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goto set_EPC;
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case EXCP_IBE:
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cause = 6;
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goto set_EPC;
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case EXCP_DBE:
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cause = 7;
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goto set_EPC;
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case EXCP_SYSCALL:
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cause = 8;
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goto set_EPC;
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case EXCP_BREAK:
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cause = 9;
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goto set_EPC;
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case EXCP_RI:
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cause = 10;
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goto set_EPC;
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case EXCP_CpU:
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cause = 11;
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env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
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(env->error_code << CP0Ca_CE);
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goto set_EPC;
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case EXCP_OVERFLOW:
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cause = 12;
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goto set_EPC;
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case EXCP_TRAP:
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cause = 13;
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goto set_EPC;
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case EXCP_FPE:
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cause = 15;
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goto set_EPC;
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case EXCP_C2E:
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cause = 18;
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goto set_EPC;
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case EXCP_MDMX:
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cause = 22;
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goto set_EPC;
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case EXCP_DWATCH:
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cause = 23;
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/* XXX: TODO: manage defered watch exceptions */
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goto set_EPC;
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case EXCP_MCHECK:
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cause = 24;
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goto set_EPC;
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case EXCP_THREAD:
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cause = 25;
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goto set_EPC;
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case EXCP_CACHE:
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cause = 30;
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if (env->CP0_Status & (1 << CP0St_BEV)) {
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offset = 0x100;
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} else {
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offset = 0x20000100;
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}
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set_EPC:
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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goto enter_debug_mode;
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case EXCP_DINT:
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env->CP0_Debug |= 1 << CP0DB_DINT;
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goto set_DEPC;
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case EXCP_DIB:
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env->CP0_Debug |= 1 << CP0DB_DIB;
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goto set_DEPC;
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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goto set_DEPC;
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_EPC = env->active_tc.PC - 4;
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->CP0_DEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_EPC = env->active_tc.PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_DEPC = env->active_tc.PC;
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}
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env->CP0_Status |= (1 << CP0St_EXL);
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00480;
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break;
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case EXCP_RESET:
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cpu_reset(env);
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break;
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case EXCP_SRESET:
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env->CP0_Status |= (1 << CP0St_SR);
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memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
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goto set_error_EPC;
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case EXCP_NMI:
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env->CP0_Status |= (1 << CP0St_NMI);
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set_error_EPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_ErrorEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_ErrorEPC = env->active_tc.PC;
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}
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00000;
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break;
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case EXCP_EXT_INTERRUPT:
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cause = 0;
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if (env->CP0_Cause & (1 << CP0Ca_IV))
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offset = 0x200;
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goto set_EPC;
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case EXCP_LTLBL:
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cause = 1;
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goto set_EPC;
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case EXCP_TLBL:
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cause = 2;
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
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#if defined(TARGET_MIPS64)
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int R = env->CP0_BadVAddr >> 62;
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
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offset = 0x080;
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else
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#endif
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offset = 0x000;
|
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}
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goto set_EPC;
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case EXCP_TLBS:
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cause = 3;
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if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
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#if defined(TARGET_MIPS64)
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int R = env->CP0_BadVAddr >> 62;
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
|
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
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offset = 0x080;
|
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else
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#endif
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offset = 0x000;
|
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}
|
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goto set_EPC;
|
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case EXCP_AdEL:
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cause = 4;
|
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goto set_EPC;
|
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case EXCP_AdES:
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cause = 5;
|
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goto set_EPC;
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case EXCP_IBE:
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cause = 6;
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goto set_EPC;
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case EXCP_DBE:
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cause = 7;
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goto set_EPC;
|
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case EXCP_SYSCALL:
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cause = 8;
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goto set_EPC;
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case EXCP_BREAK:
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cause = 9;
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goto set_EPC;
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case EXCP_RI:
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cause = 10;
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goto set_EPC;
|
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case EXCP_CpU:
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cause = 11;
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env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
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(env->error_code << CP0Ca_CE);
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goto set_EPC;
|
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case EXCP_OVERFLOW:
|
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cause = 12;
|
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goto set_EPC;
|
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case EXCP_TRAP:
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cause = 13;
|
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goto set_EPC;
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case EXCP_FPE:
|
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cause = 15;
|
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goto set_EPC;
|
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case EXCP_C2E:
|
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cause = 18;
|
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goto set_EPC;
|
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case EXCP_MDMX:
|
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cause = 22;
|
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goto set_EPC;
|
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case EXCP_DWATCH:
|
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cause = 23;
|
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/* XXX: TODO: manage defered watch exceptions */
|
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goto set_EPC;
|
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case EXCP_MCHECK:
|
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cause = 24;
|
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goto set_EPC;
|
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case EXCP_THREAD:
|
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cause = 25;
|
||||
goto set_EPC;
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case EXCP_CACHE:
|
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cause = 30;
|
||||
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
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offset = 0x100;
|
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} else {
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offset = 0x20000100;
|
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}
|
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set_EPC:
|
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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if (env->hflags & MIPS_HFLAG_BMASK) {
|
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/* If the exception was raised from a delay slot,
|
||||
come back to the jump. */
|
||||
env->CP0_EPC = env->active_tc.PC - 4;
|
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env->CP0_Cause |= (1 << CP0Ca_BD);
|
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} else {
|
||||
env->CP0_EPC = env->active_tc.PC;
|
||||
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
||||
}
|
||||
env->CP0_Status |= (1 << CP0St_EXL);
|
||||
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
|
||||
env->hflags &= ~(MIPS_HFLAG_KSU);
|
||||
}
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
||||
env->active_tc.PC = (int32_t)0xBFC00200;
|
||||
} else {
|
||||
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
||||
}
|
||||
env->active_tc.PC += offset;
|
||||
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
||||
break;
|
||||
default:
|
||||
if (logfile) {
|
||||
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
||||
env->exception_index);
|
||||
}
|
||||
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
||||
exit(1);
|
||||
}
|
||||
env->hflags &= ~MIPS_HFLAG_BMASK;
|
||||
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
||||
env->active_tc.PC = (int32_t)0xBFC00200;
|
||||
} else {
|
||||
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
||||
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
||||
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
|
||||
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
|
||||
__func__, env->active_tc.PC, env->CP0_EPC, cause,
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
|
||||
env->CP0_DEPC);
|
||||
}
|
||||
env->active_tc.PC += offset;
|
||||
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
||||
break;
|
||||
default:
|
||||
if (logfile) {
|
||||
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
||||
env->exception_index);
|
||||
}
|
||||
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
||||
exit(1);
|
||||
}
|
||||
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
||||
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
|
||||
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
|
||||
__func__, env->active_tc.PC, env->CP0_EPC, cause,
|
||||
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
|
||||
env->CP0_DEPC);
|
||||
}
|
||||
#endif /* !defined(CONFIG_USER_ONLY) */
|
||||
env->exception_index = EXCP_NONE;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue