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sun4u: split IOMMU device out from apb.c to sun4u_iommu.c
By separating the sun4u IOMMU device into new sun4u_iommu.c and sun4m_iommu.h files we noticeably simplify apb.c whilst bringing sun4u in line with all the other IOMMU-supporting architectures. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Mark Cave-Ayland
parent
aea5b07101
commit
0ea833c249
6 changed files with 403 additions and 329 deletions
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@ -49,16 +49,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define APB_DPRINTF(fmt, ...)
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#endif
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/* debug IOMMU */
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//#define DEBUG_IOMMU
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#ifdef DEBUG_IOMMU
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#define IOMMU_DPRINTF(fmt, ...) \
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do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define IOMMU_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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@ -136,211 +126,6 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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return &is->iommu_as;
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}
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/* Called from RCU critical section */
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static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr,
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IOMMUAccessFlags flag)
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{
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IOMMUState *is = container_of(iommu, IOMMUState, iommu);
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hwaddr baseaddr, offset;
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uint64_t tte;
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uint32_t tsbsize;
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = 0,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
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/* IOMMU disabled, passthrough using standard 8K page */
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ret.iova = addr & IOMMU_PAGE_MASK_8K;
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ret.translated_addr = addr;
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ret.addr_mask = IOMMU_PAGE_MASK_8K;
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ret.perm = IOMMU_RW;
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return ret;
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}
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baseaddr = is->regs[IOMMU_BASE >> 3];
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tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
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if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
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/* 64K */
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switch (tsbsize) {
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case 0:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
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break;
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case 1:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
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break;
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case 2:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
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break;
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case 3:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
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break;
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case 4:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
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break;
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case 5:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
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break;
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default:
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/* Not implemented, error */
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return ret;
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}
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} else {
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/* 8K */
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switch (tsbsize) {
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case 0:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
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break;
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case 1:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
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break;
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case 2:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
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break;
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case 3:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
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break;
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case 4:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
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break;
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case 5:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
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break;
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case 6:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
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break;
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case 7:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
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break;
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}
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}
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tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
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MEMTXATTRS_UNSPECIFIED, NULL);
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if (!(tte & IOMMU_TTE_DATA_V)) {
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/* Invalid mapping */
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return ret;
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}
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if (tte & IOMMU_TTE_DATA_W) {
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/* Writeable */
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ret.perm = IOMMU_RW;
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} else {
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ret.perm = IOMMU_RO;
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}
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/* Extract phys */
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if (tte & IOMMU_TTE_DATA_SIZE) {
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/* 64K */
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ret.iova = addr & IOMMU_PAGE_MASK_64K;
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ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
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ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
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} else {
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/* 8K */
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ret.iova = addr & IOMMU_PAGE_MASK_8K;
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ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
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ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
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}
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return ret;
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}
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static void iommu_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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IOMMUState *is = opaque;
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IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
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" size: %d\n", addr, val, size);
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switch (addr) {
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case IOMMU_CTRL:
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if (size == 4) {
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is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
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is->regs[IOMMU_CTRL >> 3] |= val << 32;
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} else {
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is->regs[IOMMU_CTRL >> 3] = val;
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}
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break;
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case IOMMU_CTRL + 0x4:
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is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
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is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
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break;
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case IOMMU_BASE:
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if (size == 4) {
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is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
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is->regs[IOMMU_BASE >> 3] |= val << 32;
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} else {
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is->regs[IOMMU_BASE >> 3] = val;
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}
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break;
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case IOMMU_BASE + 0x4:
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is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
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is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
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break;
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case IOMMU_FLUSH:
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case IOMMU_FLUSH + 0x4:
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"apb iommu: Unimplemented register write "
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"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
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addr, size, val);
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break;
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}
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}
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static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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IOMMUState *is = opaque;
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uint64_t val;
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switch (addr) {
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case IOMMU_CTRL:
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if (size == 4) {
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val = is->regs[IOMMU_CTRL >> 3] >> 32;
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} else {
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val = is->regs[IOMMU_CTRL >> 3];
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}
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break;
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case IOMMU_CTRL + 0x4:
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val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
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break;
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case IOMMU_BASE:
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if (size == 4) {
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val = is->regs[IOMMU_BASE >> 3] >> 32;
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} else {
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val = is->regs[IOMMU_BASE >> 3];
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}
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break;
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case IOMMU_BASE + 0x4:
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val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
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break;
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case IOMMU_FLUSH:
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case IOMMU_FLUSH + 0x4:
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val = 0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"apb iommu: Unimplemented register read "
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"reg 0x%" HWADDR_PRIx " size 0x%x\n",
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addr, size);
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val = 0;
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break;
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}
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IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
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" size: %d\n", addr, val, size);
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return val;
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}
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static void apb_config_writel (void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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@ -807,69 +592,11 @@ static const TypeInfo pbm_pci_bridge_info = {
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},
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};
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static const MemoryRegionOps iommu_mem_ops = {
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.read = iommu_mem_read,
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.write = iommu_mem_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void iommu_reset(DeviceState *d)
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{
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IOMMUState *s = SUN4U_IOMMU(d);
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memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t));
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}
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static void iommu_init(Object *obj)
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{
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IOMMUState *s = SUN4U_IOMMU(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
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TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s),
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"iommu-apb", UINT64_MAX);
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address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as");
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memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
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IOMMU_NREGS * sizeof(uint64_t));
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void iommu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = iommu_reset;
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}
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static const TypeInfo pbm_iommu_info = {
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.name = TYPE_SUN4U_IOMMU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IOMMUState),
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.instance_init = iommu_init,
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.class_init = iommu_class_init,
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};
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static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data)
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{
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IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
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imrc->translate = pbm_translate_iommu;
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}
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static const TypeInfo pbm_iommu_memory_region_info = {
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.parent = TYPE_IOMMU_MEMORY_REGION,
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.name = TYPE_APB_IOMMU_MEMORY_REGION,
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.class_init = pbm_iommu_memory_region_class_init,
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};
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static void pbm_register_types(void)
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{
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type_register_static(&pbm_host_info);
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type_register_static(&pbm_pci_host_info);
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type_register_static(&pbm_pci_bridge_info);
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type_register_static(&pbm_iommu_info);
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type_register_static(&pbm_iommu_memory_region_info);
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}
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type_init(pbm_register_types)
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