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ICH9 LPC: Reset Control Register, basic implementation

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This commit does the same for the ICH9 LPC as commit 1ec4ba74 for the
PIIX3. For the present we're ignoring the Full Reset (FULL_RST) and System
Reset (SYS_RST) bits; the guest can read them back but that's it.

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Laszlo Ersek 2013-02-20 02:51:24 +01:00 • committed by Michael S. Tsirkin
parent 7feb640cf3
commit 0e98b436ec
2 changed files with 68 additions and 0 deletions
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11
hw/ich9.h
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@ -49,6 +49,15 @@ typedef struct ICH9LPCState {
/* 10.1 Chipset Configuration registers(Memory Space)
which is pointed by RCBA */
uint8_t chip_config[ICH9_CC_SIZE];
/*
* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
*
* register contents and IO memory region
*/
uint8_t rst_cnt;
MemoryRegion rst_cnt_mem;
/* isa bus */
ISABus *isa_bus;
MemoryRegion rbca_mem;
@ -103,6 +112,8 @@ typedef struct ICH9LPCState {
#define ICH9_D2P_A2_REVISION 0x92
/* D31:F0 LPC Processor Interface */
#define ICH9_RST_CNT_IOPORT 0xCF9
/* D31:F1 LPC controller */
#define ICH9_A2_LPC "ICH9 A2 LPC"