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ppc 7.0 queue:

Browse source 
* More documentation updates (Leonardo)
 * Fixes for the 7448 CPU (Fabiano and Cedric)
 * Final removal of 403 CPUs and the .load_state_old handler (Cedric)
 * More cleanups of PHB4 models (Daniel and Cedric)
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Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220118' into staging

ppc 7.0 queue:

* More documentation updates (Leonardo)
* Fixes for the 7448 CPU (Fabiano and Cedric)
* Final removal of 403 CPUs and the .load_state_old handler (Cedric)
* More cleanups of PHB4 models (Daniel and Cedric)

# gpg: Signature made Tue 18 Jan 2022 11:59:16 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-ppc-20220118: (31 commits)
  ppc/pnv: Remove PHB4 version property
  ppc/pnv: Add a 'rp_model' class attribute for the PHB4 PEC
  ppc/pnv: Move root port allocation under pnv_pec_default_phb_realize()
  ppc/pnv: rename pnv_pec_stk_update_map()
  ppc/pnv: remove PnvPhb4PecStack object
  ppc/pnv: make PECs create and realize PHB4s
  ppc/pnv: remove PnvPhb4PecStack::stack_no
  ppc/pnv: move default_phb_realize() to pec_realize()
  ppc/pnv: remove stack pointer from PnvPHB4
  ppc/pnv: reduce stack->stack_no usage
  ppc/pnv: introduce PnvPHB4 'pec' property
  ppc/pnv: move phb_regs_mr to PnvPHB4
  ppc/pnv: move nest_regs_mr to PnvPHB4
  ppc/pnv: change pnv_pec_stk_update_map() to use PnvPHB4
  ppc/pnv: move nest_regs[] to PnvPHB4
  ppc/pnv: move mmbar0/mmbar1 and friends to PnvPHB4
  ppc/pnv: change pnv_phb4_update_regions() to use PnvPHB4
  ppc/pnv: move intbar to PnvPHB4
  ppc/pnv: move phbbar to PnvPHB4
  ppc/pnv: move PCI registers to PnvPHB4
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-01-18 19:43:33 +00:00
commit 0dabdd6b3a
15 changed files with 938 additions and 945 deletions
Download patch file Download diff file Expand all files Collapse all files

295
hw/pci-host/pnv_phb4.c
View file

@ -22,7 +22,6 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#define phb_error(phb, fmt, ...) \
@ -228,16 +227,16 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
/* TODO: Figure out how to implemet/decode AOMASK */
/* Check if it matches an enabled MMIO region in the PEC stack */
if (memory_region_is_mapped(&phb->stack->mmbar0) &&
base >= phb->stack->mmio0_base &&
(base + size) <= (phb->stack->mmio0_base + phb->stack->mmio0_size)) {
parent = &phb->stack->mmbar0;
base -= phb->stack->mmio0_base;
} else if (memory_region_is_mapped(&phb->stack->mmbar1) &&
base >= phb->stack->mmio1_base &&
(base + size) <= (phb->stack->mmio1_base + phb->stack->mmio1_size)) {
parent = &phb->stack->mmbar1;
base -= phb->stack->mmio1_base;
if (memory_region_is_mapped(&phb->mmbar0) &&
base >= phb->mmio0_base &&
(base + size) <= (phb->mmio0_base + phb->mmio0_size)) {
parent = &phb->mmbar0;
base -= phb->mmio0_base;
} else if (memory_region_is_mapped(&phb->mmbar1) &&
base >= phb->mmio1_base &&
(base + size) <= (phb->mmio1_base + phb->mmio1_size)) {
parent = &phb->mmbar1;
base -= phb->mmio1_base;
} else {
phb_error(phb, "PHB MBAR %d out of parent bounds", index);
return;
@ -673,7 +672,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)
switch (off) {
case PHB_VERSION:
return phb->version;
return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;
/* Read-only */
case PHB_PHB4_GEN_CAP:
@ -861,44 +860,65 @@ const MemoryRegionOps pnv_phb4_xscom_ops = {
static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
/* TODO: add list of allowed registers and error out if not */
return stack->nest_regs[reg];
return phb->nest_regs[reg];
}
static void pnv_phb4_update_regions(PnvPhb4PecStack *stack)
/*
* Return the 'stack_no' of a PHB4. 'stack_no' is the order
* the PHB4 occupies in the PEC. This is the reverse of what
* pnv_phb4_pec_get_phb_id() does.
*
* E.g. a phb with phb_id = 4 and pec->index = 1 (PEC1) will
* be the second phb (stack_no = 1) of the PEC.
*/
static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb)
{
PnvPHB4 *phb = stack->phb;
PnvPhb4PecState *pec = phb->pec;
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
int index = pec->index;
int stack_no = phb->phb_id;
while (index--) {
stack_no -= pecc->num_phbs[index];
}
return stack_no;
}
static void pnv_phb4_update_regions(PnvPHB4 *phb)
{
/* Unmap first always */
if (memory_region_is_mapped(&phb->mr_regs)) {
memory_region_del_subregion(&stack->phbbar, &phb->mr_regs);
memory_region_del_subregion(&phb->phbbar, &phb->mr_regs);
}
if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) {
memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio);
memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio);
}
/* Map registers if enabled */
if (memory_region_is_mapped(&stack->phbbar)) {
memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs);
if (memory_region_is_mapped(&phb->phbbar)) {
memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs);
}
/* Map ESB if enabled */
if (memory_region_is_mapped(&stack->intbar)) {
memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio);
if (memory_region_is_mapped(&phb->intbar)) {
memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio);
}
/* Check/update m32 */
pnv_phb4_check_all_mbt(phb);
}
static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
static void pnv_pec_phb_update_map(PnvPHB4 *phb)
{
PnvPhb4PecState *pec = stack->pec;
PnvPhb4PecState *pec = phb->pec;
MemoryRegion *sysmem = get_system_memory();
uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN];
uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN];
int stack_no = pnv_phb4_get_phb_stack_no(phb);
uint64_t bar, mask, size;
char name[64];
@ -911,106 +931,106 @@ static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
*/
/* Handle unmaps */
if (memory_region_is_mapped(&stack->mmbar0) &&
if (memory_region_is_mapped(&phb->mmbar0) &&
!(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
memory_region_del_subregion(sysmem, &stack->mmbar0);
memory_region_del_subregion(sysmem, &phb->mmbar0);
}
if (memory_region_is_mapped(&stack->mmbar1) &&
if (memory_region_is_mapped(&phb->mmbar1) &&
!(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
memory_region_del_subregion(sysmem, &stack->mmbar1);
memory_region_del_subregion(sysmem, &phb->mmbar1);
}
if (memory_region_is_mapped(&stack->phbbar) &&
if (memory_region_is_mapped(&phb->phbbar) &&
!(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
memory_region_del_subregion(sysmem, &stack->phbbar);
memory_region_del_subregion(sysmem, &phb->phbbar);
}
if (memory_region_is_mapped(&stack->intbar) &&
if (memory_region_is_mapped(&phb->intbar) &&
!(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
memory_region_del_subregion(sysmem, &stack->intbar);
memory_region_del_subregion(sysmem, &phb->intbar);
}
/* Update PHB */
pnv_phb4_update_regions(stack);
pnv_phb4_update_regions(phb);
/* Handle maps */
if (!memory_region_is_mapped(&stack->mmbar0) &&
if (!memory_region_is_mapped(&phb->mmbar0) &&
(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
size = ((~mask) >> 8) + 1;
snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0",
pec->chip_id, pec->index, stack->stack_no);
memory_region_init(&stack->mmbar0, OBJECT(stack), name, size);
memory_region_add_subregion(sysmem, bar, &stack->mmbar0);
stack->mmio0_base = bar;
stack->mmio0_size = size;
snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio0",
pec->chip_id, pec->index, stack_no);
memory_region_init(&phb->mmbar0, OBJECT(phb), name, size);
memory_region_add_subregion(sysmem, bar, &phb->mmbar0);
phb->mmio0_base = bar;
phb->mmio0_size = size;
}
if (!memory_region_is_mapped(&stack->mmbar1) &&
if (!memory_region_is_mapped(&phb->mmbar1) &&
(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
size = ((~mask) >> 8) + 1;
snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1",
pec->chip_id, pec->index, stack->stack_no);
memory_region_init(&stack->mmbar1, OBJECT(stack), name, size);
memory_region_add_subregion(sysmem, bar, &stack->mmbar1);
stack->mmio1_base = bar;
stack->mmio1_size = size;
snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio1",
pec->chip_id, pec->index, stack_no);
memory_region_init(&phb->mmbar1, OBJECT(phb), name, size);
memory_region_add_subregion(sysmem, bar, &phb->mmbar1);
phb->mmio1_base = bar;
phb->mmio1_size = size;
}
if (!memory_region_is_mapped(&stack->phbbar) &&
if (!memory_region_is_mapped(&phb->phbbar) &&
(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
size = PNV_PHB4_NUM_REGS << 3;
snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb",
pec->chip_id, pec->index, stack->stack_no);
memory_region_init(&stack->phbbar, OBJECT(stack), name, size);
memory_region_add_subregion(sysmem, bar, &stack->phbbar);
snprintf(name, sizeof(name), "pec-%d.%d-phb-%d",
pec->chip_id, pec->index, stack_no);
memory_region_init(&phb->phbbar, OBJECT(phb), name, size);
memory_region_add_subregion(sysmem, bar, &phb->phbbar);
}
if (!memory_region_is_mapped(&stack->intbar) &&
if (!memory_region_is_mapped(&phb->intbar) &&
(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
size = PNV_PHB4_MAX_INTs << 16;
snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int",
stack->pec->chip_id, stack->pec->index, stack->stack_no);
memory_region_init(&stack->intbar, OBJECT(stack), name, size);
memory_region_add_subregion(sysmem, bar, &stack->intbar);
snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int",
phb->pec->chip_id, phb->pec->index, stack_no);
memory_region_init(&phb->intbar, OBJECT(phb), name, size);
memory_region_add_subregion(sysmem, bar, &phb->intbar);
}
/* Update PHB */
pnv_phb4_update_regions(stack);
pnv_phb4_update_regions(phb);
}
static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
PnvPhb4PecState *pec = stack->pec;
PnvPHB4 *phb = PNV_PHB4(opaque);
PnvPhb4PecState *pec = phb->pec;
uint32_t reg = addr >> 3;
switch (reg) {
case PEC_NEST_STK_PCI_NEST_FIR:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_CLR:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_SET:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSK:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKS:
stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
stack->nest_regs[reg] = val;
phb->nest_regs[reg] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_WOF:
stack->nest_regs[reg] = 0;
phb->nest_regs[reg] = 0;
break;
case PEC_NEST_STK_ERR_REPORT_0:
case PEC_NEST_STK_ERR_REPORT_1:
@ -1018,39 +1038,39 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
/* Flag error ? */
break;
case PEC_NEST_STK_PBCQ_MODE:
stack->nest_regs[reg] = val & 0xff00000000000000ull;
phb->nest_regs[reg] = val & 0xff00000000000000ull;
break;
case PEC_NEST_STK_MMIO_BAR0:
case PEC_NEST_STK_MMIO_BAR0_MASK:
case PEC_NEST_STK_MMIO_BAR1:
case PEC_NEST_STK_MMIO_BAR1_MASK:
if (stack->nest_regs[PEC_NEST_STK_BAR_EN] &
if (phb->nest_regs[PEC_NEST_STK_BAR_EN] &
(PEC_NEST_STK_BAR_EN_MMIO0 |
PEC_NEST_STK_BAR_EN_MMIO1)) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
stack->nest_regs[reg] = val & 0xffffffffff000000ull;
phb->nest_regs[reg] = val & 0xffffffffff000000ull;
break;
case PEC_NEST_STK_PHB_REGS_BAR:
if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
stack->nest_regs[reg] = val & 0xffffffffffc00000ull;
phb->nest_regs[reg] = val & 0xffffffffffc00000ull;
break;
case PEC_NEST_STK_INT_BAR:
if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
stack->nest_regs[reg] = val & 0xfffffff000000000ull;
phb->nest_regs[reg] = val & 0xfffffff000000000ull;
break;
case PEC_NEST_STK_BAR_EN:
stack->nest_regs[reg] = val & 0xf000000000000000ull;
pnv_pec_stk_update_map(stack);
phb->nest_regs[reg] = val & 0xf000000000000000ull;
pnv_pec_phb_update_map(phb);
break;
case PEC_NEST_STK_DATA_FRZ_TYPE:
case PEC_NEST_STK_PBCQ_TUN_BAR:
/* Not used for now */
stack->nest_regs[reg] = val;
phb->nest_regs[reg] = val;
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
@ -1071,54 +1091,54 @@ static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
/* TODO: add list of allowed registers and error out if not */
return stack->pci_regs[reg];
return phb->pci_regs[reg];
}
static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
switch (reg) {
case PEC_PCI_STK_PCI_FIR:
stack->pci_regs[reg] = val;
phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_CLR:
stack->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
break;
case PEC_PCI_STK_PCI_FIR_SET:
stack->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
break;
case PEC_PCI_STK_PCI_FIR_MSK:
stack->pci_regs[reg] = val;
phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_MSKC:
stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
break;
case PEC_PCI_STK_PCI_FIR_MSKS:
stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
break;
case PEC_PCI_STK_PCI_FIR_ACT0:
case PEC_PCI_STK_PCI_FIR_ACT1:
stack->pci_regs[reg] = val;
phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_WOF:
stack->pci_regs[reg] = 0;
phb->pci_regs[reg] = 0;
break;
case PEC_PCI_STK_ETU_RESET:
stack->pci_regs[reg] = val & 0x8000000000000000ull;
phb->pci_regs[reg] = val & 0x8000000000000000ull;
/* TODO: Implement reset */
break;
case PEC_PCI_STK_PBAIB_ERR_REPORT:
break;
case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
stack->pci_regs[reg] = val;
phb->pci_regs[reg] = val;
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
@ -1362,7 +1382,7 @@ int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index)
int offset = 0;
while (index--) {
offset += pecc->num_stacks[index];
offset += pecc->num_phbs[index];
}
return offset + stack_index;
@ -1459,9 +1479,9 @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn)
static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
{
PnvPhb4PecStack *stack = phb->stack;
PnvPhb4PecState *pec = stack->pec;
PnvPhb4PecState *pec = phb->pec;
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
int stack_no = pnv_phb4_get_phb_stack_no(phb);
uint32_t pec_nest_base;
uint32_t pec_pci_base;
char name[64];
@ -1469,22 +1489,22 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
assert(pec);
/* Initialize the XSCOM regions for the stack registers */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d",
pec->chip_id, pec->index, stack->stack_no);
pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack),
&pnv_pec_stk_nest_xscom_ops, stack, name,
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-phb-%d",
pec->chip_id, pec->index, stack_no);
pnv_xscom_region_init(&phb->nest_regs_mr, OBJECT(phb),
&pnv_pec_stk_nest_xscom_ops, phb, name,
PHB4_PEC_NEST_STK_REGS_COUNT);
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d",
pec->chip_id, pec->index, stack->stack_no);
pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack),
&pnv_pec_stk_pci_xscom_ops, stack, name,
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
pec->chip_id, pec->index, stack_no);
pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb),
&pnv_pec_stk_pci_xscom_ops, phb, name,
PHB4_PEC_PCI_STK_REGS_COUNT);
/* PHB pass-through */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb",
pec->chip_id, pec->index, stack->stack_no);
pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb),
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
pec->chip_id, pec->index, stack_no);
pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb),
&pnv_phb4_xscom_ops, phb, name, 0x40);
pec_nest_base = pecc->xscom_nest_base(pec);
@ -1492,15 +1512,15 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
/* Populate the XSCOM address space. */
pnv_xscom_add_subregion(pec->chip,
pec_nest_base + 0x40 * (stack->stack_no + 1),
&stack->nest_regs_mr);
pec_nest_base + 0x40 * (stack_no + 1),
&phb->nest_regs_mr);
pnv_xscom_add_subregion(pec->chip,
pec_pci_base + 0x40 * (stack->stack_no + 1),
&stack->pci_regs_mr);
pec_pci_base + 0x40 * (stack_no + 1),
&phb->pci_regs_mr);
pnv_xscom_add_subregion(pec->chip,
pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
0x40 * stack->stack_no,
&stack->phb_regs_mr);
0x40 * stack_no,
&phb->phb_regs_mr);
}
static void pnv_phb4_instance_init(Object *obj)
@ -1513,8 +1533,8 @@ static void pnv_phb4_instance_init(Object *obj)
object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
}
static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb,
Error **errp)
static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
int chip_id = phb->chip_id;
@ -1523,14 +1543,14 @@ static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb,
for (i = 0; i < chip->num_pecs; i++) {
/*
* For each PEC, check the amount of stacks it supports
* and see if the given phb4 index matches a stack.
* For each PEC, check the amount of phbs it supports
* and see if the given phb4 index matches an index.
*/
PnvPhb4PecState *pec = &chip9->pecs[i];
for (j = 0; j < pec->num_stacks; j++) {
for (j = 0; j < pec->num_phbs; j++) {
if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
return &pec->stacks[j];
return pec;
}
}
}
@ -1552,10 +1572,9 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
char name[32];
/* User created PHB */
if (!phb->stack) {
if (!phb->pec) {
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
PnvPhb4PecClass *pecc;
BusState *s;
if (!chip) {
@ -1563,23 +1582,12 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
return;
}
phb->stack = pnv_phb4_get_stack(chip, phb, &local_err);
phb->pec = pnv_phb4_get_pec(chip, phb, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
/* All other phb properties but 'version' are already set */
pecc = PNV_PHB4_PEC_GET_CLASS(phb->stack->pec);
object_property_set_int(OBJECT(phb), "version", pecc->version,
&error_fatal);
/*
* Assign stack->phb since pnv_phb4_update_regions() uses it
* to access the phb.
*/
phb->stack->phb = phb;
/*
* Reparent user created devices to the chip to build
* correctly the device tree.
@ -1624,12 +1632,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
/* Add a single Root port if running with defaults */
if (defaults_enabled()) {
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
TYPE_PNV_PHB4_ROOT_PORT);
}
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
@ -1680,9 +1682,8 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno)
static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
DEFINE_PROP_UINT64("version", PnvPHB4, version, 0),
DEFINE_PROP_LINK("stack", PnvPHB4, stack, TYPE_PNV_PHB4_PEC_STACK,
PnvPhb4PecStack *),
DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
PnvPhb4PecState *),
DEFINE_PROP_END_OF_LIST(),
};

121
hw/pci-host/pnv_phb4_pec.c
View file

@ -112,15 +112,28 @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
static void pnv_pec_instance_init(Object *obj)
static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
int stack_no,
Error **errp)
{
PnvPhb4PecState *pec = PNV_PHB4_PEC(obj);
int i;
PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) {
object_initialize_child(obj, "stack[*]", &pec->stacks[i],
TYPE_PNV_PHB4_PEC_STACK);
object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
&error_abort);
object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
&error_fatal);
object_property_set_int(OBJECT(phb), "index", phb_id,
&error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
return;
}
/* Add a single Root port if running with defaults */
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
PNV_PHB4_PEC_GET_CLASS(pec)->rp_model);
}
static void pnv_pec_realize(DeviceState *dev, Error **errp)
@ -135,22 +148,14 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
return;
}
pec->num_stacks = pecc->num_stacks[pec->index];
pec->num_phbs = pecc->num_phbs[pec->index];
/* Create stacks */
for (i = 0; i < pec->num_stacks; i++) {
PnvPhb4PecStack *stack = &pec->stacks[i];
Object *stk_obj = OBJECT(stack);
object_property_set_int(stk_obj, "stack-no", i, &error_abort);
object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort);
if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) {
return;
/* Create PHBs if running with defaults */
if (defaults_enabled()) {
for (i = 0; i < pec->num_phbs; i++) {
pnv_pec_default_phb_realize(pec, i, errp);
}
}
for (; i < PHB4_PEC_MAX_STACKS; i++) {
object_unparent(OBJECT(&pec->stacks[i]));
}
/* Initialize the XSCOM regions for the PEC registers */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
@ -195,7 +200,7 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
_FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
pecc->compat_size)));
for (i = 0; i < pec->num_stacks; i++) {
for (i = 0; i < pec->num_phbs; i++) {
int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
int stk_offset;
@ -231,11 +236,11 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
}
/*
* PEC0 -> 1 stack
* PEC1 -> 2 stacks
* PEC2 -> 3 stacks
* PEC0 -> 1 phb
* PEC1 -> 2 phb
* PEC2 -> 3 phbs
*/
static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 };
static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
static void pnv_pec_class_init(ObjectClass *klass, void *data)
{
@ -260,14 +265,14 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->stk_compat = stk_compat;
pecc->stk_compat_size = sizeof(stk_compat);
pecc->version = PNV_PHB4_VERSION;
pecc->num_stacks = pnv_pec_num_stacks;
pecc->num_phbs = pnv_pec_num_phbs;
pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
}
static const TypeInfo pnv_pec_type_info = {
.name = TYPE_PNV_PHB4_PEC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPhb4PecState),
.instance_init = pnv_pec_instance_init,
.class_init = pnv_pec_class_init,
.class_size = sizeof(PnvPhb4PecClass),
.interfaces = (InterfaceInfo[]) {
@ -276,73 +281,9 @@ static const TypeInfo pnv_pec_type_info = {
}
};
static void pnv_pec_stk_default_phb_realize(PnvPhb4PecStack *stack,
Error **errp)
{
PnvPhb4PecState *pec = stack->pec;
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no);
stack->phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id,
&error_fatal);
object_property_set_int(OBJECT(stack->phb), "index", phb_id,
&error_fatal);
object_property_set_int(OBJECT(stack->phb), "version", pecc->version,
&error_fatal);
object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) {
return;
}
}
static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev);
if (!defaults_enabled()) {
return;
}
pnv_pec_stk_default_phb_realize(stack, errp);
}
static Property pnv_pec_stk_properties[] = {
DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0),
DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC,
PnvPhb4PecState *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_pec_stk_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_props(dc, pnv_pec_stk_properties);
dc->realize = pnv_pec_stk_realize;
dc->user_creatable = false;
/* TODO: reset regs ? */
}
static const TypeInfo pnv_pec_stk_type_info = {
.name = TYPE_PNV_PHB4_PEC_STACK,
.parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPhb4PecStack),
.class_init = pnv_pec_stk_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_PNV_XSCOM_INTERFACE },
{ }
}
};
static void pnv_pec_register_types(void)
{
type_register_static(&pnv_pec_type_info);
type_register_static(&pnv_pec_stk_type_info);
}
type_init(pnv_pec_register_types);