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linux-headers: Update to Linux v6.12-rc5

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update linux-headers to v6.12-rc5. Pass to compile on aarch64, arm,
loongarch64, x86_64, i386, riscv64,riscv32 softmmu and linux-user.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20241028023809.1554405-4-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao 2024-10-28 10:38:09 +08:00 • committed by Song Gao
parent d394a09cc1
commit 0d2eeef77a
29 changed files with 1915 additions and 93 deletions
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41
include/standard-headers/linux/pci_regs.h
View file

@ -634,9 +634,11 @@
#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */
#define PCI_EXP_RTCTL_CRSSVE PCI_EXP_RTCTL_RRS_SVE /* compatibility */
#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
#define PCI_EXP_RTCAP_RRS_SV 0x0001 /* Config RRS Software Visibility */
#define PCI_EXP_RTCAP_CRSVIS PCI_EXP_RTCAP_RRS_SV /* compatibility */
#define PCI_EXP_RTSTA 0x20 /* Root Status */
#define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
@ -740,6 +742,7 @@
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
@ -1121,6 +1124,40 @@
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
/* Native PCIe Enclosure Management */
#define PCI_NPEM_CAP 0x04 /* NPEM capability register */
#define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */
#define PCI_NPEM_CTRL 0x08 /* NPEM control register */
#define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */
/*
* Native PCIe Enclosure Management indication bits and Reset command bit
* are corresponding for capability and control registers.
*/
#define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */
#define PCI_NPEM_IND_OK 0x00000004 /* OK */
#define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */
#define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */
#define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */
#define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */
#define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */
#define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */
#define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */
#define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */
#define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */
#define PCI_NPEM_IND_SPEC_0 0x01000000
#define PCI_NPEM_IND_SPEC_1 0x02000000
#define PCI_NPEM_IND_SPEC_2 0x04000000
#define PCI_NPEM_IND_SPEC_3 0x08000000
#define PCI_NPEM_IND_SPEC_4 0x10000000
#define PCI_NPEM_IND_SPEC_5 0x20000000
#define PCI_NPEM_IND_SPEC_6 0x40000000
#define PCI_NPEM_IND_SPEC_7 0x80000000
#define PCI_NPEM_STATUS 0x0c /* NPEM status register */
#define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */
/* Data Object Exchange */
#define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */
#define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */