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https://github.com/Motorhead1991/qemu.git
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linux-headers: Update to Linux v6.12-rc5
update linux-headers to v6.12-rc5. Pass to compile on aarch64, arm, loongarch64, x86_64, i386, riscv64,riscv32 softmmu and linux-user. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20241028023809.1554405-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao
Song Gao
parent
d394a09cc1
commit
0d2eeef77a
29 changed files with 1915 additions and 93 deletions
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@ -701,6 +701,31 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
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/*
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* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
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* on integrated graphics
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all compressible GEM objects.
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*/
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#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
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/*
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* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
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* on discrete graphics
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all compressible GEM objects. The GEM object must be stored in
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* contiguous memory with a size aligned to 64KB
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*/
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#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -1475,6 +1500,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
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#define AMD_FMT_MOD_TILE_VER_GFX10 2
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#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
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#define AMD_FMT_MOD_TILE_VER_GFX11 4
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#define AMD_FMT_MOD_TILE_VER_GFX12 5
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/*
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* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
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@ -1485,6 +1511,8 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
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/*
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* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
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* GFX9 as canonical version.
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*
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* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
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*/
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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@ -1492,6 +1520,21 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
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/* Gfx12 swizzle modes:
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* 0 - LINEAR
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* 1 - 256B_2D - 2D block dimensions
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* 2 - 4KB_2D
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* 3 - 64KB_2D
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* 4 - 256KB_2D
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* 5 - 4KB_3D - 3D block dimensions
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* 6 - 64KB_3D
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* 7 - 256KB_3D
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*/
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#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
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#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
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#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
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#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
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#define AMD_FMT_MOD_DCC_BLOCK_64B 0
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#define AMD_FMT_MOD_DCC_BLOCK_128B 1
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#define AMD_FMT_MOD_DCC_BLOCK_256B 2
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@ -28,6 +28,23 @@
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#define _BITUL(x) (_UL(1) << (x))
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#define _BITULL(x) (_ULL(1) << (x))
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#if !defined(__ASSEMBLY__)
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/*
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* Missing __asm__ support
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*
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* __BIT128() would not work in the __asm__ code, as it shifts an
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* 'unsigned __init128' data type as direct representation of
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* 128 bit constants is not supported in the gcc compiler, as
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* they get silently truncated.
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*
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* TODO: Please revisit this implementation when gcc compiler
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* starts representing 128 bit constants directly like long
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* and unsigned long etc. Subsequently drop the comment for
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* GENMASK_U128() which would then start supporting __asm__ code.
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*/
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#define _BIT128(x) ((unsigned __int128)(1) << (x))
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#endif
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#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1)
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#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask))
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@ -752,6 +752,197 @@ enum ethtool_module_power_mode {
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ETHTOOL_MODULE_POWER_MODE_HIGH,
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};
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/**
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* enum ethtool_c33_pse_ext_state - groups of PSE extended states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION: Group of error_condition states
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* @ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID: Group of mr_mps_valid states
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* @ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE: Group of mr_pse_enable states
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* @ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED: Group of option_detect_ted
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* states
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* @ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM: Group of option_vport_lim states
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* @ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED: Group of ovld_detected states
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* @ETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE: Group of pd_dll_power_type
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* states
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* @ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE: Group of power_not_available
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* states
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* @ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED: Group of short_detected states
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*/
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enum ethtool_c33_pse_ext_state {
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ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1,
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ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID,
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ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE,
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ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED,
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ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
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ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED,
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ETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE,
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ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
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ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_mr_mps_valid - mr_mps_valid states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD: Underload
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* state
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN: Port is not
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* connected
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*
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* The PSE monitors either the DC or AC Maintain Power Signature
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* (MPS, see 33.2.9.1). This variable indicates the presence or absence of
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* a valid MPS.
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*/
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enum ethtool_c33_pse_ext_substate_mr_mps_valid {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD = 1,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_error_condition - error_condition states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT: Non-existing
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* port number
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT: Undefined port
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT: Internal
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* hardware fault
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON:
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* Communication error after force on
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS: Unknown
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* port status
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF: Host
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* crash turn off
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN:
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* Host crash force shutdown
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE: Configuration
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* change
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP: Over
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* temperature detected
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*
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* error_condition is a variable indicating the status of
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* implementation-specific fault conditions or optionally other system faults
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* that prevent the PSE from meeting the specifications in Table 33–11 and that
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* require the PSE not to source power. These error conditions are different
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* from those monitored by the state diagrams in Figure 33–10.
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*/
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enum ethtool_c33_pse_ext_substate_error_condition {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_mr_pse_enable - mr_pse_enable states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE: Disable
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* pin active
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*
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* mr_pse_enable is control variable that selects PSE operation and test
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* functions.
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*/
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enum ethtool_c33_pse_ext_substate_mr_pse_enable {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_option_detect_ted - option_detect_ted
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* states functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS: Detection
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* in process
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR:
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* Connection check error
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*
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* option_detect_ted is a variable indicating if detection can be performed
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* by the PSE during the ted_timer interval.
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*/
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enum ethtool_c33_pse_ext_substate_option_detect_ted {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_option_vport_lim - option_vport_lim states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE: Main supply
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* voltage is high
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE: Main supply
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* voltage is low
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION: Voltage
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* injection into the port
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*
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* option_vport_lim is an optional variable indicates if VPSE is out of the
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* operating range during normal operating state.
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*/
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enum ethtool_c33_pse_ext_substate_option_vport_lim {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_ovld_detected - ovld_detected states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD: Overload state
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*
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* ovld_detected is a variable indicating if the PSE output current has been
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* in an overload condition (see 33.2.7.6) for at least TCUT of a one-second
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* sliding time.
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*/
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enum ethtool_c33_pse_ext_substate_ovld_detected {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_power_not_available - power_not_available
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* states functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED: Power
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* budget exceeded for the controller
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET:
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* Configured port power limit exceeded controller power budget
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT:
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* Power request from PD exceeds port limit
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT: Power
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* denied due to Hardware power limit
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*
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* power_not_available is a variable that is asserted in an
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* implementation-dependent manner when the PSE is no longer capable of
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* sourcing sufficient power to support the attached PD. Sufficient power
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* is defined by classification; see 33.2.6.
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*/
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enum ethtool_c33_pse_ext_substate_power_not_available {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT,
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ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT,
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};
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/**
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* enum ethtool_c33_pse_ext_substate_short_detected - short_detected states
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* functions. IEEE 802.3-2022 33.2.4.4 Variables
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*
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* @ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION: Short
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* condition was detected
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*
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* short_detected is a variable indicating if the PSE output current has been
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* in a short circuit condition for TLIM within a sliding window (see 33.2.7.7).
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*/
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enum ethtool_c33_pse_ext_substate_short_detected {
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ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1,
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};
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/**
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* enum ethtool_pse_types - Types of PSE controller.
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* @ETHTOOL_PSE_UNKNOWN: Type of PSE controller is unknown
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@ -877,6 +1068,24 @@ enum ethtool_mm_verify_status {
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ETHTOOL_MM_VERIFY_STATUS_DISABLED,
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};
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/**
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* enum ethtool_module_fw_flash_status - plug-in module firmware flashing status
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* @ETHTOOL_MODULE_FW_FLASH_STATUS_STARTED: The firmware flashing process has
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* started.
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* @ETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS: The firmware flashing process
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* is in progress.
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* @ETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED: The firmware flashing process was
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* completed successfully.
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* @ETHTOOL_MODULE_FW_FLASH_STATUS_ERROR: The firmware flashing process was
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* stopped due to an error.
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*/
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enum ethtool_module_fw_flash_status {
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ETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1,
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ETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS,
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ETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED,
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ETHTOOL_MODULE_FW_FLASH_STATUS_ERROR,
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};
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/**
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* struct ethtool_gstrings - string set for data tagging
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* @cmd: Command number = %ETHTOOL_GSTRINGS
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@ -1845,6 +2054,7 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,
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ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,
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ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,
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ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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@ -2323,4 +2533,20 @@ struct ethtool_link_settings {
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* uint32_t map_lp_advertising[link_mode_masks_nwords];
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*/
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};
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/**
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* enum phy_upstream - Represents the upstream component a given PHY device
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||||
* is connected to, as in what is on the other end of the MII bus. Most PHYs
|
||||
* will be attached to an Ethernet MAC controller, but in some cases, there's
|
||||
* an intermediate PHY used as a media-converter, which will driver another
|
||||
* MII interface as its output.
|
||||
* @PHY_UPSTREAM_MAC: Upstream component is a MAC (a switch port,
|
||||
* or ethernet controller)
|
||||
* @PHY_UPSTREAM_PHY: Upstream component is a PHY (likely a media converter)
|
||||
*/
|
||||
enum phy_upstream {
|
||||
PHY_UPSTREAM_MAC,
|
||||
PHY_UPSTREAM_PHY,
|
||||
};
|
||||
|
||||
#endif /* _LINUX_ETHTOOL_H */
|
||||
|
|
|
|||
|
|
@ -217,6 +217,9 @@
|
|||
* - add backing_id to fuse_open_out, add FOPEN_PASSTHROUGH open flag
|
||||
* - add FUSE_NO_EXPORT_SUPPORT init flag
|
||||
* - add FUSE_NOTIFY_RESEND, add FUSE_HAS_RESEND init flag
|
||||
*
|
||||
* 7.41
|
||||
* - add FUSE_ALLOW_IDMAP
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_FUSE_H
|
||||
|
|
@ -248,7 +251,7 @@
|
|||
#define FUSE_KERNEL_VERSION 7
|
||||
|
||||
/** Minor version number of this interface */
|
||||
#define FUSE_KERNEL_MINOR_VERSION 40
|
||||
#define FUSE_KERNEL_MINOR_VERSION 41
|
||||
|
||||
/** The node ID of the root inode */
|
||||
#define FUSE_ROOT_ID 1
|
||||
|
|
@ -417,6 +420,7 @@ struct fuse_file_lock {
|
|||
* FUSE_NO_EXPORT_SUPPORT: explicitly disable export support
|
||||
* FUSE_HAS_RESEND: kernel supports resending pending requests, and the high bit
|
||||
* of the request ID indicates resend requests
|
||||
* FUSE_ALLOW_IDMAP: allow creation of idmapped mounts
|
||||
*/
|
||||
#define FUSE_ASYNC_READ (1 << 0)
|
||||
#define FUSE_POSIX_LOCKS (1 << 1)
|
||||
|
|
@ -462,6 +466,7 @@ struct fuse_file_lock {
|
|||
|
||||
/* Obsolete alias for FUSE_DIRECT_IO_ALLOW_MMAP */
|
||||
#define FUSE_DIRECT_IO_RELAX FUSE_DIRECT_IO_ALLOW_MMAP
|
||||
#define FUSE_ALLOW_IDMAP (1ULL << 40)
|
||||
|
||||
/**
|
||||
* CUSE INIT request/reply flags
|
||||
|
|
@ -980,6 +985,21 @@ struct fuse_fallocate_in {
|
|||
*/
|
||||
#define FUSE_UNIQUE_RESEND (1ULL << 63)
|
||||
|
||||
/**
|
||||
* This value will be set by the kernel to
|
||||
* (struct fuse_in_header).{uid,gid} fields in
|
||||
* case when:
|
||||
* - fuse daemon enabled FUSE_ALLOW_IDMAP
|
||||
* - idmapping information is not available and uid/gid
|
||||
* can not be mapped in accordance with an idmapping.
|
||||
*
|
||||
* Note: an idmapping information always available
|
||||
* for inode creation operations like:
|
||||
* FUSE_MKNOD, FUSE_SYMLINK, FUSE_MKDIR, FUSE_TMPFILE,
|
||||
* FUSE_CREATE and FUSE_RENAME2 (with RENAME_WHITEOUT).
|
||||
*/
|
||||
#define FUSE_INVALID_UIDGID ((uint32_t)(-1))
|
||||
|
||||
struct fuse_in_header {
|
||||
uint32_t len;
|
||||
uint32_t opcode;
|
||||
|
|
|
|||
|
|
@ -618,6 +618,8 @@
|
|||
#define KEY_CAMERA_ACCESS_ENABLE 0x24b /* Enables programmatic access to camera devices. (HUTRR72) */
|
||||
#define KEY_CAMERA_ACCESS_DISABLE 0x24c /* Disables programmatic access to camera devices. (HUTRR72) */
|
||||
#define KEY_CAMERA_ACCESS_TOGGLE 0x24d /* Toggles the current state of the camera access control. (HUTRR72) */
|
||||
#define KEY_ACCESSIBILITY 0x24e /* Toggles the system bound accessibility UI/command (HUTRR116) */
|
||||
#define KEY_DO_NOT_DISTURB 0x24f /* Toggles the system-wide "Do Not Disturb" control (HUTRR94)*/
|
||||
|
||||
#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
|
||||
#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
|
||||
|
|
|
|||
|
|
@ -634,9 +634,11 @@
|
|||
#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
|
||||
#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
|
||||
#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
|
||||
#define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */
|
||||
#define PCI_EXP_RTCTL_CRSSVE PCI_EXP_RTCTL_RRS_SVE /* compatibility */
|
||||
#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
|
||||
#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
|
||||
#define PCI_EXP_RTCAP_RRS_SV 0x0001 /* Config RRS Software Visibility */
|
||||
#define PCI_EXP_RTCAP_CRSVIS PCI_EXP_RTCAP_RRS_SV /* compatibility */
|
||||
#define PCI_EXP_RTSTA 0x20 /* Root Status */
|
||||
#define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */
|
||||
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
|
||||
|
|
@ -740,6 +742,7 @@
|
|||
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
|
||||
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
|
||||
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
|
||||
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
|
||||
#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
|
||||
#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
|
||||
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
|
||||
|
|
@ -1121,6 +1124,40 @@
|
|||
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
|
||||
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
|
||||
|
||||
/* Native PCIe Enclosure Management */
|
||||
#define PCI_NPEM_CAP 0x04 /* NPEM capability register */
|
||||
#define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */
|
||||
|
||||
#define PCI_NPEM_CTRL 0x08 /* NPEM control register */
|
||||
#define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */
|
||||
|
||||
/*
|
||||
* Native PCIe Enclosure Management indication bits and Reset command bit
|
||||
* are corresponding for capability and control registers.
|
||||
*/
|
||||
#define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */
|
||||
#define PCI_NPEM_IND_OK 0x00000004 /* OK */
|
||||
#define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */
|
||||
#define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */
|
||||
#define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */
|
||||
#define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */
|
||||
#define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */
|
||||
#define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */
|
||||
#define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */
|
||||
#define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */
|
||||
#define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */
|
||||
#define PCI_NPEM_IND_SPEC_0 0x01000000
|
||||
#define PCI_NPEM_IND_SPEC_1 0x02000000
|
||||
#define PCI_NPEM_IND_SPEC_2 0x04000000
|
||||
#define PCI_NPEM_IND_SPEC_3 0x08000000
|
||||
#define PCI_NPEM_IND_SPEC_4 0x10000000
|
||||
#define PCI_NPEM_IND_SPEC_5 0x20000000
|
||||
#define PCI_NPEM_IND_SPEC_6 0x40000000
|
||||
#define PCI_NPEM_IND_SPEC_7 0x80000000
|
||||
|
||||
#define PCI_NPEM_STATUS 0x0c /* NPEM status register */
|
||||
#define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */
|
||||
|
||||
/* Data Object Exchange */
|
||||
#define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */
|
||||
#define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */
|
||||
|
|
|
|||
|
|
@ -71,7 +71,13 @@ struct virtio_balloon_config {
|
|||
#define VIRTIO_BALLOON_S_CACHES 7 /* Disk caches */
|
||||
#define VIRTIO_BALLOON_S_HTLB_PGALLOC 8 /* Hugetlb page allocations */
|
||||
#define VIRTIO_BALLOON_S_HTLB_PGFAIL 9 /* Hugetlb page allocation failures */
|
||||
#define VIRTIO_BALLOON_S_NR 10
|
||||
#define VIRTIO_BALLOON_S_OOM_KILL 10 /* OOM killer invocations */
|
||||
#define VIRTIO_BALLOON_S_ALLOC_STALL 11 /* Stall count of memory allocatoin */
|
||||
#define VIRTIO_BALLOON_S_ASYNC_SCAN 12 /* Amount of memory scanned asynchronously */
|
||||
#define VIRTIO_BALLOON_S_DIRECT_SCAN 13 /* Amount of memory scanned directly */
|
||||
#define VIRTIO_BALLOON_S_ASYNC_RECLAIM 14 /* Amount of memory reclaimed asynchronously */
|
||||
#define VIRTIO_BALLOON_S_DIRECT_RECLAIM 15 /* Amount of memory reclaimed directly */
|
||||
#define VIRTIO_BALLOON_S_NR 16
|
||||
|
||||
#define VIRTIO_BALLOON_S_NAMES_WITH_PREFIX(VIRTIO_BALLOON_S_NAMES_prefix) { \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "swap-in", \
|
||||
|
|
@ -83,7 +89,13 @@ struct virtio_balloon_config {
|
|||
VIRTIO_BALLOON_S_NAMES_prefix "available-memory", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "disk-caches", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "hugetlb-allocations", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "hugetlb-failures" \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "hugetlb-failures", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "oom-kills", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "alloc-stalls", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "async-scans", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "direct-scans", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "async-reclaims", \
|
||||
VIRTIO_BALLOON_S_NAMES_prefix "direct-reclaims" \
|
||||
}
|
||||
|
||||
#define VIRTIO_BALLOON_S_NAMES VIRTIO_BALLOON_S_NAMES_WITH_PREFIX("")
|
||||
|
|
|
|||
|
|
@ -311,6 +311,7 @@ struct virtio_gpu_cmd_submit {
|
|||
#define VIRTIO_GPU_CAPSET_VIRGL2 2
|
||||
/* 3 is reserved for gfxstream */
|
||||
#define VIRTIO_GPU_CAPSET_VENUS 4
|
||||
#define VIRTIO_GPU_CAPSET_DRM 6
|
||||
|
||||
/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
|
||||
struct virtio_gpu_get_capset_info {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue