motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Add csr support for svadu

Browse source 
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-24 12:08:49 +08:00 • committed by Palmer Dabbelt
parent 6f3eb1a3c8
commit 0d190bd394
No known key found for this signature in database
GPG key ID: 2E1319F35FBB1889
3 changed files with 16 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

1
target/riscv/cpu.h
View file

@ -450,6 +450,7 @@ struct RISCVCPUConfig {
bool ext_zihintpause; bool ext_zihintpause;
bool ext_smstateen; bool ext_smstateen;
bool ext_sstc; bool ext_sstc;
bool ext_svadu;
bool ext_svinval; bool ext_svinval;
bool ext_svnapot; bool ext_svnapot;
bool ext_svpbmt; bool ext_svpbmt;

4
target/riscv/cpu_bits.h
View file

@ -747,10 +747,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7) #define MENVCFG_CBZE BIT(7)
#define MENVCFG_HADE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63) #define MENVCFG_STCE (1ULL << 63)
/* For RV32 */ /* For RV32 */
#define MENVCFGH_HADE BIT(29)
#define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31) #define MENVCFGH_STCE BIT(31)
@ -763,10 +765,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE #define HENVCFG_CBZE MENVCFG_CBZE
#define HENVCFG_HADE MENVCFG_HADE
#define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE #define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */ /* For RV32 */
#define HENVCFGH_HADE MENVCFGH_HADE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE #define HENVCFGH_STCE MENVCFGH_STCE

17
target/riscv/csr.c
View file

@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) { if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0); (cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0);
} }
env->menvcfg = (env->menvcfg & ~mask) | (val & mask); env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
{ {
RISCVCPUConfig *cfg = &env_archcpu(env)->cfg; RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0); (cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0);
uint64_t valh = (uint64_t)val << 32; uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
/* /*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
* henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/ */
*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg); *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
env->menvcfg);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
} }
if (riscv_cpu_mxl(env) == MXL_RV64) { if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE); mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
} }
env->henvcfg = (env->henvcfg & ~mask) | (val & mask); env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
return ret; return ret;
} }
*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
env->menvcfg)) >> 32; env->menvcfg)) >> 32;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE); uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
HENVCFG_HADE);
uint64_t valh = (uint64_t)val << 32; uint64_t valh = (uint64_t)val << 32;
RISCVException ret; RISCVException ret;