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exec: introduce memory_ldst.inc.c
Templatize the address_space_* and *_phys functions, so that we can add similar functions in the next patch that work with a lightweight, cache-like version of address_space_map/unmap. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
2651efe7f5
commit
0ce265ffef
4 changed files with 734 additions and 686 deletions
681
exec.c
681
exec.c
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@ -3058,677 +3058,16 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
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}
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/* warning: addr must be aligned */
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static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs,
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MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, false);
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if (l < 4 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldl_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldl_be_p(ptr);
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break;
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default:
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val = ldl_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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return val;
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}
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uint32_t address_space_ldl(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldl_internal(as, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldl_internal(as, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldl_internal(as, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint32_t ldl_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs,
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MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 8;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l,
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false);
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if (l < 8 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap64(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap64(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldq_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldq_be_p(ptr);
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break;
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default:
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val = ldq_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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return val;
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}
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uint64_t address_space_ldq(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldq_internal(as, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldq_internal(as, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_ldq_internal(as, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint64_t ldq_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t address_space_ldub(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, false);
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if (!memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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val = ldub_p(ptr);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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return val;
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}
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uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline uint32_t address_space_lduw_internal(AddressSpace *as,
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hwaddr addr,
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MemTxAttrs attrs,
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MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l,
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false);
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if (l < 2 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap16(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = lduw_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = lduw_be_p(ptr);
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break;
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default:
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val = lduw_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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return val;
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}
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uint32_t address_space_lduw(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_lduw_internal(as, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_lduw_internal(as, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result)
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{
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return address_space_lduw_internal(as, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint32_t lduw_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr)
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{
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return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned. The ram page is not masked as dirty
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and the code inside is not invalidated. It is useful if the dirty
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bits are used to track modified PTEs */
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void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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uint8_t dirty_log_mask;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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} else {
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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stl_p(ptr, val);
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dirty_log_mask = memory_region_get_dirty_log_mask(mr);
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dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
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cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
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4, dirty_log_mask);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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}
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void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline void address_space_stl_internal(AddressSpace *as,
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hwaddr addr, uint32_t val,
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MemTxAttrs attrs,
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MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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stl_le_p(ptr, val);
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break;
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case DEVICE_BIG_ENDIAN:
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stl_be_p(ptr, val);
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break;
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default:
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stl_p(ptr, val);
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break;
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}
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invalidate_and_set_dirty(mr, addr1, 4);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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rcu_read_unlock();
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}
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void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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address_space_stl_internal(as, addr, val, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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address_space_stl_internal(as, addr, val, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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address_space_stl_internal(as, addr, val, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr1, &l, true);
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if (!memory_access_is_direct(mr, true)) {
|
||||
release_lock |= prepare_mmio_access(mr);
|
||||
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
|
||||
} else {
|
||||
/* RAM case */
|
||||
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
|
||||
stb_p(ptr, val);
|
||||
invalidate_and_set_dirty(mr, addr1, 1);
|
||||
r = MEMTX_OK;
|
||||
}
|
||||
if (result) {
|
||||
*result = r;
|
||||
}
|
||||
if (release_lock) {
|
||||
qemu_mutex_unlock_iothread();
|
||||
}
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
|
||||
{
|
||||
address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
/* warning: addr must be aligned */
|
||||
static inline void address_space_stw_internal(AddressSpace *as,
|
||||
hwaddr addr, uint32_t val,
|
||||
MemTxAttrs attrs,
|
||||
MemTxResult *result,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
MemoryRegion *mr;
|
||||
hwaddr l = 2;
|
||||
hwaddr addr1;
|
||||
MemTxResult r;
|
||||
bool release_lock = false;
|
||||
|
||||
rcu_read_lock();
|
||||
mr = address_space_translate(as, addr, &addr1, &l, true);
|
||||
if (l < 2 || !memory_access_is_direct(mr, true)) {
|
||||
release_lock |= prepare_mmio_access(mr);
|
||||
|
||||
#if defined(TARGET_WORDS_BIGENDIAN)
|
||||
if (endian == DEVICE_LITTLE_ENDIAN) {
|
||||
val = bswap16(val);
|
||||
}
|
||||
#else
|
||||
if (endian == DEVICE_BIG_ENDIAN) {
|
||||
val = bswap16(val);
|
||||
}
|
||||
#endif
|
||||
r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
|
||||
} else {
|
||||
/* RAM case */
|
||||
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
|
||||
switch (endian) {
|
||||
case DEVICE_LITTLE_ENDIAN:
|
||||
stw_le_p(ptr, val);
|
||||
break;
|
||||
case DEVICE_BIG_ENDIAN:
|
||||
stw_be_p(ptr, val);
|
||||
break;
|
||||
default:
|
||||
stw_p(ptr, val);
|
||||
break;
|
||||
}
|
||||
invalidate_and_set_dirty(mr, addr1, 2);
|
||||
r = MEMTX_OK;
|
||||
}
|
||||
if (result) {
|
||||
*result = r;
|
||||
}
|
||||
if (release_lock) {
|
||||
qemu_mutex_unlock_iothread();
|
||||
}
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stw_internal(as, addr, val, attrs, result,
|
||||
DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stw_internal(as, addr, val, attrs, result,
|
||||
DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stw_internal(as, addr, val, attrs, result,
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val)
|
||||
{
|
||||
address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val)
|
||||
{
|
||||
address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
|
||||
{
|
||||
address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
static inline void address_space_stq_internal(AddressSpace *as,
|
||||
hwaddr addr, uint64_t val,
|
||||
MemTxAttrs attrs,
|
||||
MemTxResult *result,
|
||||
enum device_endian endian)
|
||||
{
|
||||
uint8_t *ptr;
|
||||
MemoryRegion *mr;
|
||||
hwaddr l = 8;
|
||||
hwaddr addr1;
|
||||
MemTxResult r;
|
||||
bool release_lock = false;
|
||||
|
||||
rcu_read_lock();
|
||||
mr = address_space_translate(as, addr, &addr1, &l, true);
|
||||
if (l < 8 || !memory_access_is_direct(mr, true)) {
|
||||
release_lock |= prepare_mmio_access(mr);
|
||||
|
||||
#if defined(TARGET_WORDS_BIGENDIAN)
|
||||
if (endian == DEVICE_LITTLE_ENDIAN) {
|
||||
val = bswap64(val);
|
||||
}
|
||||
#else
|
||||
if (endian == DEVICE_BIG_ENDIAN) {
|
||||
val = bswap64(val);
|
||||
}
|
||||
#endif
|
||||
r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
|
||||
} else {
|
||||
/* RAM case */
|
||||
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
|
||||
switch (endian) {
|
||||
case DEVICE_LITTLE_ENDIAN:
|
||||
stq_le_p(ptr, val);
|
||||
break;
|
||||
case DEVICE_BIG_ENDIAN:
|
||||
stq_be_p(ptr, val);
|
||||
break;
|
||||
default:
|
||||
stq_p(ptr, val);
|
||||
break;
|
||||
}
|
||||
invalidate_and_set_dirty(mr, addr1, 8);
|
||||
r = MEMTX_OK;
|
||||
}
|
||||
if (result) {
|
||||
*result = r;
|
||||
}
|
||||
if (release_lock) {
|
||||
qemu_mutex_unlock_iothread();
|
||||
}
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stq_internal(as, addr, val, attrs, result,
|
||||
DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stq_internal(as, addr, val, attrs, result,
|
||||
DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val,
|
||||
MemTxAttrs attrs, MemTxResult *result)
|
||||
{
|
||||
address_space_stq_internal(as, addr, val, attrs, result,
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
|
||||
{
|
||||
address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
|
||||
{
|
||||
address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
|
||||
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
|
||||
{
|
||||
address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
|
||||
}
|
||||
#define ARG1_DECL AddressSpace *as
|
||||
#define ARG1 as
|
||||
#define SUFFIX
|
||||
#define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
|
||||
#define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
|
||||
#define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
|
||||
#define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
|
||||
#define RCU_READ_LOCK(...) rcu_read_lock()
|
||||
#define RCU_READ_UNLOCK(...) rcu_read_unlock()
|
||||
#include "memory_ldst.inc.c"
|
||||
|
||||
/* virtual memory access for debug (includes writing to ROM) */
|
||||
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue