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RISC-V: Add trailing '\n' to qemu_log() calls

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Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180606152128.449-11-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2018-06-08 13:15:33 +01:00 • committed by Peter Maydell
parent 21528149eb
commit 0cd3f644fe
1 changed files with 4 additions and 2 deletions
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6
target/riscv/op_helper.c
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@ -293,7 +293,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
if ((val_to_write & 3) == 0) { if ((val_to_write & 3) == 0) {
env->stvec = val_to_write >> 2 << 2; env->stvec = val_to_write >> 2 << 2;
} else { } else {
qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); qemu_log_mask(LOG_UNIMP,
"CSR_STVEC: vectored traps not supported\n");
} }
break; break;
case CSR_SCOUNTEREN: case CSR_SCOUNTEREN:
@ -320,7 +321,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
if ((val_to_write & 3) == 0) { if ((val_to_write & 3) == 0) {
env->mtvec = val_to_write >> 2 << 2; env->mtvec = val_to_write >> 2 << 2;
} else { } else {
qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); qemu_log_mask(LOG_UNIMP,
"CSR_MTVEC: vectored traps not supported\n");
} }
break; break;
case CSR_MCOUNTEREN: case CSR_MCOUNTEREN: