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cputlb: move TLB handling to a separate file
Move TLB handling and softmmu code load helpers to cputlb.c, compile only for softmmu targets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Blue Swirl
parent
e554861766
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5 changed files with 443 additions and 376 deletions
362
cputlb.c
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362
cputlb.c
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/*
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* Common CPU TLB handling
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "cpu.h"
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#include "exec-all.h"
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#include "memory.h"
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#include "cputlb.h"
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#define WANT_EXEC_OBSOLETE
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#include "exec-obsolete.h"
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//#define DEBUG_TLB
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//#define DEBUG_TLB_CHECK
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/* statistics */
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int tlb_flush_count;
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static const CPUTLBEntry s_cputlb_empty_entry = {
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.addr_read = -1,
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.addr_write = -1,
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.addr_code = -1,
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.addend = -1,
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};
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/* NOTE:
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* If flush_global is true (the usual case), flush all tlb entries.
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* If flush_global is false, flush (at least) all tlb entries not
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* marked global.
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*
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* Since QEMU doesn't currently implement a global/not-global flag
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* for tlb entries, at the moment tlb_flush() will also flush all
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* tlb entries in the flush_global == false case. This is OK because
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* CPU architectures generally permit an implementation to drop
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* entries from the TLB at any time, so flushing more entries than
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* required is only an efficiency issue, not a correctness issue.
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*/
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void tlb_flush(CPUArchState *env, int flush_global)
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{
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int i;
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#if defined(DEBUG_TLB)
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printf("tlb_flush:\n");
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#endif
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/* must reset current TB so that interrupts cannot modify the
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links while we are modifying them */
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env->current_tb = NULL;
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for (i = 0; i < CPU_TLB_SIZE; i++) {
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int mmu_idx;
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
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}
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}
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memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
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env->tlb_flush_addr = -1;
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env->tlb_flush_mask = 0;
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tlb_flush_count++;
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}
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static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
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{
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if (addr == (tlb_entry->addr_read &
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(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
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addr == (tlb_entry->addr_write &
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(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
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addr == (tlb_entry->addr_code &
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(TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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*tlb_entry = s_cputlb_empty_entry;
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}
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}
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void tlb_flush_page(CPUArchState *env, target_ulong addr)
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{
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int i;
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int mmu_idx;
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#if defined(DEBUG_TLB)
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printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
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#endif
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/* Check if we need to flush due to large pages. */
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if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
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#if defined(DEBUG_TLB)
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printf("tlb_flush_page: forced full flush ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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env->tlb_flush_addr, env->tlb_flush_mask);
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#endif
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tlb_flush(env, 1);
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return;
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}
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/* must reset current TB so that interrupts cannot modify the
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links while we are modifying them */
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env->current_tb = NULL;
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addr &= TARGET_PAGE_MASK;
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i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
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}
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tb_flush_jmp_cache(env, addr);
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}
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/* update the TLBs so that writes to code in the virtual page 'addr'
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can be detected */
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void tlb_protect_code(ram_addr_t ram_addr)
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{
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cpu_physical_memory_reset_dirty(ram_addr,
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ram_addr + TARGET_PAGE_SIZE,
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CODE_DIRTY_FLAG);
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}
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/* update the TLB so that writes in physical page 'phys_addr' are no longer
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tested for self modifying code */
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void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
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target_ulong vaddr)
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{
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cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
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}
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static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
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{
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return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
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}
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void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
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uintptr_t length)
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{
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uintptr_t addr;
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if (tlb_is_dirty_ram(tlb_entry)) {
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addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
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if ((addr - start) < length) {
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tlb_entry->addr_write |= TLB_NOTDIRTY;
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}
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}
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}
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static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
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{
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ram_addr_t ram_addr;
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void *p;
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if (tlb_is_dirty_ram(tlb_entry)) {
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p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
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+ tlb_entry->addend);
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ram_addr = qemu_ram_addr_from_host_nofail(p);
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if (!cpu_physical_memory_is_dirty(ram_addr)) {
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tlb_entry->addr_write |= TLB_NOTDIRTY;
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}
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}
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}
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void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
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{
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CPUArchState *env;
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for (env = first_cpu; env != NULL; env = env->next_cpu) {
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int mmu_idx;
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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unsigned int i;
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for (i = 0; i < CPU_TLB_SIZE; i++) {
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tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
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start1, length);
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}
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}
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}
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}
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static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
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{
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if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
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tlb_entry->addr_write = vaddr;
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}
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}
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/* update the TLB corresponding to virtual page vaddr
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so that it is no longer dirty */
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void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
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{
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int i;
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int mmu_idx;
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vaddr &= TARGET_PAGE_MASK;
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i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
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}
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}
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/* Our TLB does not support large pages, so remember the area covered by
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large pages and trigger a full TLB flush if these are invalidated. */
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static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
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target_ulong size)
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{
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target_ulong mask = ~(size - 1);
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if (env->tlb_flush_addr == (target_ulong)-1) {
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env->tlb_flush_addr = vaddr & mask;
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env->tlb_flush_mask = mask;
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return;
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}
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/* Extend the existing region to include the new page.
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This is a compromise between unnecessary flushes and the cost
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of maintaining a full variable size TLB. */
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mask &= env->tlb_flush_mask;
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while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
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mask <<= 1;
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}
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env->tlb_flush_addr &= mask;
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env->tlb_flush_mask = mask;
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}
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/* Add a new TLB entry. At most one entry for a given virtual address
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is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
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supplied size is only used by tlb_flush_page. */
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void tlb_set_page(CPUArchState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, target_ulong size)
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{
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MemoryRegionSection *section;
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unsigned int index;
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target_ulong address;
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target_ulong code_address;
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uintptr_t addend;
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CPUTLBEntry *te;
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target_phys_addr_t iotlb;
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assert(size >= TARGET_PAGE_SIZE);
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if (size != TARGET_PAGE_SIZE) {
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tlb_add_large_page(env, vaddr, size);
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}
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section = phys_page_find(paddr >> TARGET_PAGE_BITS);
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#if defined(DEBUG_TLB)
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printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
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" prot=%x idx=%d pd=0x%08lx\n",
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vaddr, paddr, prot, mmu_idx, pd);
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#endif
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address = vaddr;
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if (!is_ram_rom_romd(section)) {
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/* IO memory case (romd handled later) */
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address |= TLB_MMIO;
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}
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if (is_ram_rom_romd(section)) {
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addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
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+ section_addr(section, paddr);
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} else {
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addend = 0;
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}
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iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,
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&address);
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code_address = address;
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index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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env->iotlb[mmu_idx][index] = iotlb - vaddr;
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te = &env->tlb_table[mmu_idx][index];
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te->addend = addend - vaddr;
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if (prot & PAGE_READ) {
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te->addr_read = address;
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} else {
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te->addr_read = -1;
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}
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if (prot & PAGE_EXEC) {
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te->addr_code = code_address;
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} else {
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te->addr_code = -1;
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}
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if (prot & PAGE_WRITE) {
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if ((memory_region_is_ram(section->mr) && section->readonly)
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|| is_romd(section)) {
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/* Write access calls the I/O callback. */
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te->addr_write = address | TLB_MMIO;
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} else if (memory_region_is_ram(section->mr)
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&& !cpu_physical_memory_is_dirty(
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section->mr->ram_addr
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+ section_addr(section, paddr))) {
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te->addr_write = address | TLB_NOTDIRTY;
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} else {
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te->addr_write = address;
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}
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} else {
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te->addr_write = -1;
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}
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}
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/* NOTE: this function can trigger an exception */
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/* NOTE2: the returned address is not exactly the physical address: it
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is the offset relative to phys_ram_base */
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tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
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{
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int mmu_idx, page_index, pd;
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void *p;
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MemoryRegion *mr;
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page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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mmu_idx = cpu_mmu_index(env1);
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if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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(addr & TARGET_PAGE_MASK))) {
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#ifdef CONFIG_TCG_PASS_AREG0
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cpu_ldub_code(env1, addr);
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#else
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ldub_code(addr);
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#endif
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}
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pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
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mr = iotlb_to_region(pd);
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if (memory_region_is_unassigned(mr)) {
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#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
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cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
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#else
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cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
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TARGET_FMT_lx "\n", addr);
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#endif
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}
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p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
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return qemu_ram_addr_from_host_nofail(p);
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}
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#define MMUSUFFIX _cmmu
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#undef GETPC
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#define GETPC() ((uintptr_t)0)
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#define env cpu_single_env
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#define SOFTMMU_CODE_ACCESS
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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#undef env
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