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Use float32/64 instead of float/double
The patch below uses the float32 and float64 types instead of the float and double types in the PPC code. This doesn't change anything when using softfloat-native as the types are the same, but that helps compiling the PPC target with softfloat. It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and use them instead of identical unions that are defined in numerous places. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
6b59fc74b5
commit
0ca9d3807c
6 changed files with 240 additions and 457 deletions
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@ -455,53 +455,41 @@ void do_popcntb_64 (void)
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/*****************************************************************************/
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/* Floating point operations helpers */
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static always_inline int fpisneg (float64 f)
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static always_inline int fpisneg (float64 d)
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{
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union {
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float64 f;
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uint64_t u;
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} u;
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CPU_DoubleU u;
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u.f = f;
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u.d = d;
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return u.u >> 63 != 0;
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return u.ll >> 63 != 0;
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}
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static always_inline int isden (float f)
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static always_inline int isden (float64 d)
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{
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union {
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float64 f;
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uint64_t u;
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} u;
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CPU_DoubleU u;
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u.f = f;
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u.d = d;
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return ((u.u >> 52) & 0x7FF) == 0;
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return ((u.ll >> 52) & 0x7FF) == 0;
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}
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static always_inline int iszero (float64 f)
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static always_inline int iszero (float64 d)
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{
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union {
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float64 f;
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uint64_t u;
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} u;
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CPU_DoubleU u;
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u.f = f;
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u.d = d;
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return (u.u & ~0x8000000000000000ULL) == 0;
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return (u.ll & ~0x8000000000000000ULL) == 0;
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}
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static always_inline int isinfinity (float64 f)
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static always_inline int isinfinity (float64 d)
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{
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union {
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float64 f;
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uint64_t u;
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} u;
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CPU_DoubleU u;
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u.f = f;
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u.d = d;
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return ((u.u >> 52) & 0x7FF) == 0x7FF &&
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(u.u & 0x000FFFFFFFFFFFFFULL) == 0;
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return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
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(u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
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}
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void do_compute_fprf (int set_fprf)
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@ -638,10 +626,7 @@ static always_inline void fload_invalid_op_excp (int op)
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static always_inline void float_zero_divide_excp (void)
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{
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union {
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float64 f;
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uint64_t u;
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} u0, u1;
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CPU_DoubleU u0, u1;
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env->fpscr |= 1 << FPSCR_ZX;
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env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
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@ -656,11 +641,11 @@ static always_inline void float_zero_divide_excp (void)
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}
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} else {
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/* Set the result to infinity */
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u0.f = FT0;
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u1.f = FT1;
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u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
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u0.u |= 0x7FFULL << 52;
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FT0 = u0.f;
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u0.d = FT0;
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u1.d = FT1;
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u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
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u0.ll |= 0x7FFULL << 52;
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FT0 = u0.d;
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}
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}
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@ -865,18 +850,13 @@ void do_store_fpscr (uint32_t mask)
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/*
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* We use only the 32 LSB of the incoming fpr
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*/
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union {
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double d;
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struct {
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uint32_t u[2];
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} s;
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} u;
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CPU_DoubleU u;
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uint32_t prev, new;
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int i;
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u.d = FT0;
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prev = env->fpscr;
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new = u.s.u[WORD1];
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new = u.l.lower;
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new &= ~0x90000000;
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new |= prev & 0x90000000;
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for (i = 0; i < 7; i++) {
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@ -992,10 +972,7 @@ void do_fdiv (void)
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void do_fctiw (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN conversion */
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@ -1004,12 +981,12 @@ void do_fctiw (void)
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/* qNan / infinity conversion */
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fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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p.i = float64_to_int32(FT0, &env->fp_status);
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p.ll = float64_to_int32(FT0, &env->fp_status);
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#if USE_PRECISE_EMULATION
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PowerPC 750
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*/
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p.i |= 0xFFF80000ULL << 32;
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p.ll |= 0xFFF80000ULL << 32;
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#endif
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FT0 = p.d;
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}
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@ -1017,10 +994,7 @@ void do_fctiw (void)
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void do_fctiwz (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN conversion */
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@ -1029,12 +1003,12 @@ void do_fctiwz (void)
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/* qNan / infinity conversion */
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fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
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p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
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#if USE_PRECISE_EMULATION
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PowerPC 750
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*/
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p.i |= 0xFFF80000ULL << 32;
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p.ll |= 0xFFF80000ULL << 32;
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#endif
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FT0 = p.d;
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}
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@ -1043,21 +1017,15 @@ void do_fctiwz (void)
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#if defined(TARGET_PPC64)
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void do_fcfid (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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p.d = FT0;
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FT0 = int64_to_float64(p.i, &env->fp_status);
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FT0 = int64_to_float64(p.ll, &env->fp_status);
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}
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void do_fctid (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN conversion */
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@ -1066,17 +1034,14 @@ void do_fctid (void)
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/* qNan / infinity conversion */
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fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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p.i = float64_to_int64(FT0, &env->fp_status);
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p.ll = float64_to_int64(FT0, &env->fp_status);
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FT0 = p.d;
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}
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}
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void do_fctidz (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN conversion */
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@ -1085,7 +1050,7 @@ void do_fctidz (void)
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/* qNan / infinity conversion */
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fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
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} else {
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p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
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p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
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FT0 = p.d;
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}
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}
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@ -1271,10 +1236,7 @@ void do_fsqrt (void)
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void do_fre (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN reciprocal */
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@ -1286,16 +1248,16 @@ void do_fre (void)
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FT0 = float64_div(1.0, FT0, &env->fp_status);
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} else {
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p.d = FT0;
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if (p.i == 0x8000000000000000ULL) {
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p.i = 0xFFF0000000000000ULL;
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} else if (p.i == 0x0000000000000000ULL) {
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p.i = 0x7FF0000000000000ULL;
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if (p.ll == 0x8000000000000000ULL) {
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p.ll = 0xFFF0000000000000ULL;
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} else if (p.ll == 0x0000000000000000ULL) {
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p.ll = 0x7FF0000000000000ULL;
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} else if (isnan(FT0)) {
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p.i = 0x7FF8000000000000ULL;
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p.ll = 0x7FF8000000000000ULL;
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} else if (fpisneg(FT0)) {
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p.i = 0x8000000000000000ULL;
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p.ll = 0x8000000000000000ULL;
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} else {
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p.i = 0x0000000000000000ULL;
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p.ll = 0x0000000000000000ULL;
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}
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FT0 = p.d;
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}
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@ -1303,10 +1265,7 @@ void do_fre (void)
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void do_fres (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN reciprocal */
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@ -1323,16 +1282,16 @@ void do_fres (void)
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#endif
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} else {
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p.d = FT0;
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if (p.i == 0x8000000000000000ULL) {
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p.i = 0xFFF0000000000000ULL;
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} else if (p.i == 0x0000000000000000ULL) {
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p.i = 0x7FF0000000000000ULL;
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if (p.ll == 0x8000000000000000ULL) {
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p.ll = 0xFFF0000000000000ULL;
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} else if (p.ll == 0x0000000000000000ULL) {
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p.ll = 0x7FF0000000000000ULL;
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} else if (isnan(FT0)) {
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p.i = 0x7FF8000000000000ULL;
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p.ll = 0x7FF8000000000000ULL;
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} else if (fpisneg(FT0)) {
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p.i = 0x8000000000000000ULL;
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p.ll = 0x8000000000000000ULL;
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} else {
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p.i = 0x0000000000000000ULL;
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p.ll = 0x0000000000000000ULL;
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}
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FT0 = p.d;
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}
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@ -1340,10 +1299,7 @@ void do_fres (void)
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void do_frsqrte (void)
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{
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union {
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double d;
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uint64_t i;
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} p;
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CPU_DoubleU p;
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if (unlikely(float64_is_signaling_nan(FT0))) {
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/* sNaN reciprocal square root */
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@ -1356,16 +1312,16 @@ void do_frsqrte (void)
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FT0 = float32_div(1.0, FT0, &env->fp_status);
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} else {
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p.d = FT0;
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if (p.i == 0x8000000000000000ULL) {
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p.i = 0xFFF0000000000000ULL;
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} else if (p.i == 0x0000000000000000ULL) {
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p.i = 0x7FF0000000000000ULL;
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if (p.ll == 0x8000000000000000ULL) {
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p.ll = 0xFFF0000000000000ULL;
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} else if (p.ll == 0x0000000000000000ULL) {
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p.ll = 0x7FF0000000000000ULL;
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} else if (isnan(FT0)) {
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p.i |= 0x000FFFFFFFFFFFFFULL;
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p.ll |= 0x000FFFFFFFFFFFFFULL;
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} else if (fpisneg(FT0)) {
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p.i = 0x7FF8000000000000ULL;
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p.ll = 0x7FF8000000000000ULL;
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} else {
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p.i = 0x0000000000000000ULL;
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p.ll = 0x0000000000000000ULL;
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}
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FT0 = p.d;
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}
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@ -2056,36 +2012,27 @@ DO_SPE_CMP(cmpltu);
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/* Single precision floating-point conversions from/to integer */
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static always_inline uint32_t _do_efscfsi (int32_t val)
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{
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union {
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uint32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.f = int32_to_float32(val, &env->spe_status);
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return u.u;
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return u.l;
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}
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static always_inline uint32_t _do_efscfui (uint32_t val)
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{
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union {
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uint32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.f = uint32_to_float32(val, &env->spe_status);
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return u.u;
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return u.l;
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}
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static always_inline int32_t _do_efsctsi (uint32_t val)
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{
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union {
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int32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.u = val;
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u.l = val;
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/* NaN are not treated the same way IEEE 754 does */
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if (unlikely(isnan(u.f)))
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return 0;
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@ -2095,12 +2042,9 @@ static always_inline int32_t _do_efsctsi (uint32_t val)
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static always_inline uint32_t _do_efsctui (uint32_t val)
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{
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union {
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int32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.u = val;
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u.l = val;
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/* NaN are not treated the same way IEEE 754 does */
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if (unlikely(isnan(u.f)))
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return 0;
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@ -2110,12 +2054,9 @@ static always_inline uint32_t _do_efsctui (uint32_t val)
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static always_inline int32_t _do_efsctsiz (uint32_t val)
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{
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union {
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int32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.u = val;
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u.l = val;
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/* NaN are not treated the same way IEEE 754 does */
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if (unlikely(isnan(u.f)))
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return 0;
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@ -2125,12 +2066,9 @@ static always_inline int32_t _do_efsctsiz (uint32_t val)
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static always_inline uint32_t _do_efsctuiz (uint32_t val)
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{
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union {
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int32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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u.u = val;
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u.l = val;
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/* NaN are not treated the same way IEEE 754 does */
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if (unlikely(isnan(u.f)))
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return 0;
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@ -2171,43 +2109,34 @@ void do_efsctuiz (void)
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/* Single precision floating-point conversion to/from fractional */
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static always_inline uint32_t _do_efscfsf (uint32_t val)
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{
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union {
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uint32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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float32 tmp;
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u.f = int32_to_float32(val, &env->spe_status);
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tmp = int64_to_float32(1ULL << 32, &env->spe_status);
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u.f = float32_div(u.f, tmp, &env->spe_status);
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return u.u;
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return u.l;
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}
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static always_inline uint32_t _do_efscfuf (uint32_t val)
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{
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union {
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uint32_t u;
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float32 f;
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} u;
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CPU_FloatU u;
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float32 tmp;
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u.f = uint32_to_float32(val, &env->spe_status);
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tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
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u.f = float32_div(u.f, tmp, &env->spe_status);
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return u.u;
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return u.l;
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}
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static always_inline int32_t _do_efsctsf (uint32_t val)
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{
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union {
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int32_t u;
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float32 f;
|
||||
} u;
|
||||
CPU_FloatU u;
|
||||
float32 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
return 0;
|
||||
|
|
@ -2219,13 +2148,10 @@ static always_inline int32_t _do_efsctsf (uint32_t val)
|
|||
|
||||
static always_inline uint32_t _do_efsctuf (uint32_t val)
|
||||
{
|
||||
union {
|
||||
int32_t u;
|
||||
float32 f;
|
||||
} u;
|
||||
CPU_FloatU u;
|
||||
float32 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
return 0;
|
||||
|
|
@ -2237,13 +2163,10 @@ static always_inline uint32_t _do_efsctuf (uint32_t val)
|
|||
|
||||
static always_inline int32_t _do_efsctsfz (uint32_t val)
|
||||
{
|
||||
union {
|
||||
int32_t u;
|
||||
float32 f;
|
||||
} u;
|
||||
CPU_FloatU u;
|
||||
float32 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
return 0;
|
||||
|
|
@ -2255,13 +2178,10 @@ static always_inline int32_t _do_efsctsfz (uint32_t val)
|
|||
|
||||
static always_inline uint32_t _do_efsctufz (uint32_t val)
|
||||
{
|
||||
union {
|
||||
int32_t u;
|
||||
float32 f;
|
||||
} u;
|
||||
CPU_FloatU u;
|
||||
float32 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
return 0;
|
||||
|
|
@ -2338,86 +2258,68 @@ void do_efdcmpeq (void)
|
|||
/* Double precision floating-point conversion to/from integer */
|
||||
static always_inline uint64_t _do_efdcfsi (int64_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.f = int64_to_float64(val, &env->spe_status);
|
||||
u.d = int64_to_float64(val, &env->spe_status);
|
||||
|
||||
return u.u;
|
||||
return u.ll;
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdcfui (uint64_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.f = uint64_to_float64(val, &env->spe_status);
|
||||
u.d = uint64_to_float64(val, &env->spe_status);
|
||||
|
||||
return u.u;
|
||||
return u.ll;
|
||||
}
|
||||
|
||||
static always_inline int64_t _do_efdctsi (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
|
||||
return float64_to_int64(u.f, &env->spe_status);
|
||||
return float64_to_int64(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdctui (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
|
||||
return float64_to_uint64(u.f, &env->spe_status);
|
||||
return float64_to_uint64(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline int64_t _do_efdctsiz (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
|
||||
return float64_to_int64_round_to_zero(u.f, &env->spe_status);
|
||||
return float64_to_int64_round_to_zero(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdctuiz (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
|
||||
return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
|
||||
return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
void do_efdcfsi (void)
|
||||
|
|
@ -2453,104 +2355,86 @@ void do_efdctuiz (void)
|
|||
/* Double precision floating-point conversion to/from fractional */
|
||||
static always_inline uint64_t _do_efdcfsf (int64_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.f = int32_to_float64(val, &env->spe_status);
|
||||
u.d = int32_to_float64(val, &env->spe_status);
|
||||
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_div(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_div(u.d, tmp, &env->spe_status);
|
||||
|
||||
return u.u;
|
||||
return u.ll;
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdcfuf (uint64_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.f = uint32_to_float64(val, &env->spe_status);
|
||||
u.d = uint32_to_float64(val, &env->spe_status);
|
||||
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_div(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_div(u.d, tmp, &env->spe_status);
|
||||
|
||||
return u.u;
|
||||
return u.ll;
|
||||
}
|
||||
|
||||
static always_inline int64_t _do_efdctsf (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_mul(u.d, tmp, &env->spe_status);
|
||||
|
||||
return float64_to_int32(u.f, &env->spe_status);
|
||||
return float64_to_int32(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdctuf (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_mul(u.d, tmp, &env->spe_status);
|
||||
|
||||
return float64_to_uint32(u.f, &env->spe_status);
|
||||
return float64_to_uint32(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline int64_t _do_efdctsfz (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_mul(u.d, tmp, &env->spe_status);
|
||||
|
||||
return float64_to_int32_round_to_zero(u.f, &env->spe_status);
|
||||
return float64_to_int32_round_to_zero(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdctufz (uint64_t val)
|
||||
{
|
||||
union {
|
||||
int64_t u;
|
||||
float64 f;
|
||||
} u;
|
||||
CPU_DoubleU u;
|
||||
float64 tmp;
|
||||
|
||||
u.u = val;
|
||||
u.ll = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(isnan(u.f)))
|
||||
if (unlikely(isnan(u.d)))
|
||||
return 0;
|
||||
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
||||
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
||||
u.d = float64_mul(u.d, tmp, &env->spe_status);
|
||||
|
||||
return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
|
||||
return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
|
||||
}
|
||||
|
||||
void do_efdcfsf (void)
|
||||
|
|
@ -2586,36 +2470,24 @@ void do_efdctufz (void)
|
|||
/* Floating point conversion between single and double precision */
|
||||
static always_inline uint32_t _do_efscfd (uint64_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u1;
|
||||
union {
|
||||
uint32_t u;
|
||||
float32 f;
|
||||
} u2;
|
||||
CPU_DoubleU u1;
|
||||
CPU_FloatU u2;
|
||||
|
||||
u1.u = val;
|
||||
u2.f = float64_to_float32(u1.f, &env->spe_status);
|
||||
u1.ll = val;
|
||||
u2.f = float64_to_float32(u1.d, &env->spe_status);
|
||||
|
||||
return u2.u;
|
||||
return u2.l;
|
||||
}
|
||||
|
||||
static always_inline uint64_t _do_efdcfs (uint32_t val)
|
||||
{
|
||||
union {
|
||||
uint64_t u;
|
||||
float64 f;
|
||||
} u2;
|
||||
union {
|
||||
uint32_t u;
|
||||
float32 f;
|
||||
} u1;
|
||||
CPU_DoubleU u2;
|
||||
CPU_FloatU u1;
|
||||
|
||||
u1.u = val;
|
||||
u2.f = float32_to_float64(u1.f, &env->spe_status);
|
||||
u1.l = val;
|
||||
u2.d = float32_to_float64(u1.f, &env->spe_status);
|
||||
|
||||
return u2.u;
|
||||
return u2.ll;
|
||||
}
|
||||
|
||||
void do_efscfd (void)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue