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ppc/pnv: Move timebase state into PnvCore

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The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the timebase
side of the state machine to thread 0 of a core.

Move the state out into PnvCore and share it among all threads.

Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-24 21:58:18 +10:00
parent 060e614367
commit 0ca94b2f11
4 changed files with 55 additions and 50 deletions
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21
target/ppc/cpu.h
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@ -1196,21 +1196,6 @@ DEXCR_ASPECT(SRAPD, 4)
DEXCR_ASPECT(NPHIE, 5)
DEXCR_ASPECT(PHIE, 6)
/*****************************************************************************/
/* PowerNV ChipTOD and TimeBase State Machine */
struct pnv_tod_tbst {
int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
/*
* "Timers" for async TBST events are simulated by mfTFAC because TFAC
* is polled for such events. These are just used to ensure firmware
* performs the polling at least a few times.
*/
int tb_state_timer;
int tb_sync_pulse_timer;
};
/*****************************************************************************/
/* The whole PowerPC CPU context */
@ -1291,12 +1276,6 @@ struct CPUArchState {
uint32_t tlb_need_flush; /* Delayed flush needed */
#define TLB_NEED_LOCAL_FLUSH 0x1
#define TLB_NEED_GLOBAL_FLUSH 0x2
#if defined(TARGET_PPC64)
/* PowerNV chiptod / timebase facility state. */
/* Would be nice to put these into PnvCore */
struct pnv_tod_tbst pnv_tod_tbst;
#endif
#endif
/* Other registers */