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HW core patch queue

Browse source 
- Unify CPU QOM type checks (Gavin)
 - Simplify uses of some CPU related property (Philippe)
   (start-powered-off, ARM reset-cbar and mp-affinity)
 - Header and documentation cleanups (Zhao, Philippe)
 - Have Memory API return boolean indicating possible error
 - Fix frame filter mask in CAN sja1000 model (Pavel)
 - QOM embed MCF5206 timer into SoC (Thomas)
 - Simplify LEON3 qemu_irq_ack handler (Clément)
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Merge tag 'hw-cpus-20240105' of https://github.com/philmd/qemu into staging

HW core patch queue

- Unify CPU QOM type checks (Gavin)
- Simplify uses of some CPU related property (Philippe)
  (start-powered-off, ARM reset-cbar and mp-affinity)
- Header and documentation cleanups (Zhao, Philippe)
- Have Memory API return boolean indicating possible error
- Fix frame filter mask in CAN sja1000 model (Pavel)
- QOM embed MCF5206 timer into SoC (Thomas)
- Simplify LEON3 qemu_irq_ack handler (Clément)

# -----BEGIN PGP SIGNATURE-----
#
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 Jan 2024 15:41:16 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-cpus-20240105' of https://github.com/philmd/qemu: (71 commits)
  target/sparc: Simplify qemu_irq_ack
  hw/net/can/sja1000: fix bug for single acceptance filter and standard frame
  hw/m68k/mcf5206: Embed m5206_timer_state in m5206_mbar_state
  hw/pci-host/raven: Propagate error in raven_realize()
  hw/nvram: Simplify memory_region_init_rom_device() calls
  hw/misc: Simplify memory_region_init_ram_from_fd() calls
  hw/sparc: Simplify memory_region_init_ram_nomigrate() calls
  hw/arm: Simplify memory_region_init_rom() calls
  hw: Simplify memory_region_init_ram() calls
  misc: Simplify qemu_prealloc_mem() calls
  util/oslib: Have qemu_prealloc_mem() handler return a boolean
  backends: Reduce variable scope in host_memory_backend_memory_complete
  backends: Have HostMemoryBackendClass::alloc() handler return a boolean
  backends: Simplify host_memory_backend_memory_complete()
  backends: Use g_autofree in HostMemoryBackendClass::alloc() handlers
  memory: Have memory_region_init_ram_from_fd() handler return a boolean
  memory: Have memory_region_init_ram_from_file() handler return a boolean
  memory: Have memory_region_init_resizeable_ram() return a boolean
  memory: Have memory_region_init_rom_device() handler return a boolean
  memory: Simplify memory_region_init_rom_device_nomigrate() calls
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-01-05 16:08:58 +00:00
commit 0c1eccd368
105 changed files with 576 additions and 977 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/arm/armsse.c
View file

@ -1022,10 +1022,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* later if necessary.
*/
if (extract32(info->cpuwait_rst, i, 1)) {
if (!object_property_set_bool(cpuobj, "start-powered-off", true,
errp)) {
return;
}
object_property_set_bool(cpuobj, "start-powered-off", true,
&error_abort);
}
if (!s->cpu_fpu[i]) {
if (!object_property_set_bool(cpuobj, "vfp", false, errp)) {

8
hw/arm/armv7m.c
View file

@ -318,12 +318,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
return;
}
}
if (object_property_find(OBJECT(s->cpu), "start-powered-off")) {
if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off",
s->start_powered_off, errp)) {
return;
}
}
if (object_property_find(OBJECT(s->cpu), "vfp")) {
if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) {
return;
@ -334,6 +328,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
return;
}
}
object_property_set_bool(OBJECT(s->cpu), "start-powered-off",
s->start_powered_off, &error_abort);
/*
* Real M-profile hardware can be configured with a different number of

6
hw/arm/aspeed_ast2400.c
View file

@ -247,7 +247,6 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
g_autofree char *sram_name = NULL;
/* Default boot region (SPI memory or ROMs) */
@ -276,9 +275,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
errp)) {
return;
}
memory_region_add_subregion(s->memory,

6
hw/arm/aspeed_ast2600.c
View file

@ -282,7 +282,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Error *err = NULL;
qemu_irq irq;
g_autofree char *sram_name = NULL;
@ -355,9 +354,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
errp)) {
return;
}
memory_region_add_subregion(s->memory,

12
hw/arm/bananapi_m2u.c
View file

@ -71,12 +71,6 @@ static void bpim2u_init(MachineState *machine)
exit(1);
}
/* Only allow Cortex-A7 for this board */
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
error_report("This board can only be used with cortex-a7 CPU");
exit(1);
}
r40 = AW_R40(object_new(TYPE_AW_R40));
object_property_add_child(OBJECT(machine), "soc", OBJECT(r40));
object_unref(OBJECT(r40));
@ -133,12 +127,18 @@ static void bpim2u_init(MachineState *machine)
static void bpim2u_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
NULL
};
mc->desc = "Bananapi M2U (Cortex-A7)";
mc->init = bpim2u_init;
mc->min_cpus = AW_R40_NUM_CPUS;
mc->max_cpus = AW_R40_NUM_CPUS;
mc->default_cpus = AW_R40_NUM_CPUS;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "bpim2u.ram";
}

18
hw/arm/bcm2836.c
View file

@ -127,22 +127,16 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
for (n = 0; n < BCM283X_NCPUS; n++) {
/* TODO: this should be converted to a property of ARM_CPU */
s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity",
(bc->clusterid << 8) | n, &error_abort);
/* set periphbase/CBAR value for CPU-local registers */
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
bc->peri_base, errp)) {
return;
}
object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
bc->peri_base, &error_abort);
/* start powered off if not enabled */
if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
"start-powered-off",
n >= s->enabled_cpus,
errp)) {
return;
}
object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off",
n >= s->enabled_cpus, &error_abort);
if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
return;

12
hw/arm/cubieboard.c
View file

@ -52,12 +52,6 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
/* Only allow Cortex-A8 for this board */
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) != 0) {
error_report("This board can only be used with cortex-a8 CPU");
exit(1);
}
a10 = AW_A10(object_new(TYPE_AW_A10));
object_property_add_child(OBJECT(machine), "soc", OBJECT(a10));
object_unref(OBJECT(a10));
@ -114,8 +108,14 @@ static void cubieboard_init(MachineState *machine)
static void cubieboard_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a8"),
NULL
};
mc->desc = "cubietech cubieboard (Cortex-A8)";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->init = cubieboard_init;
mc->block_default_type = IF_IDE;

19
hw/arm/fsl-imx25.c
View file

@ -81,7 +81,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{
FslIMX25State *s = FSL_IMX25(dev);
uint8_t i;
Error *err = NULL;
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
return;
@ -281,28 +280,22 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
FSL_IMX25_WDT_IRQ));
/* initialize 2 x 16 KB ROM */
memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
FSL_IMX25_ROM0_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
FSL_IMX25_ROM0_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
&s->rom[0]);
memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
FSL_IMX25_ROM1_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
FSL_IMX25_ROM1_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
&s->rom[1]);
/* initialize internal RAM (128 KB) */
memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
&err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->iram, NULL, "imx25.iram",
FSL_IMX25_IRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,

19
hw/arm/fsl-imx31.c
View file

@ -63,7 +63,6 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
{
FslIMX31State *s = FSL_IMX31(dev);
uint16_t i;
Error *err = NULL;
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
return;
@ -188,30 +187,24 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
/* On a real system, the first 16k is a `secure boot rom' */
memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
FSL_IMX31_SECURE_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
FSL_IMX31_SECURE_ROM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
&s->secure_rom);
/* There is also a 16k ROM */
memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
FSL_IMX31_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
FSL_IMX31_ROM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
&s->rom);
/* initialize internal RAM (16 KB) */
memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
&err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->iram, NULL, "imx31.iram",
FSL_IMX31_IRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,

19
hw/arm/fsl-imx6.c
View file

@ -109,7 +109,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
Error *err = NULL;
unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
@ -423,30 +422,24 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
}
/* ROM memory */
memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
&s->rom);
/* CAAM memory */
memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
FSL_IMX6_CAAM_MEM_SIZE, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
FSL_IMX6_CAAM_MEM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
&s->caam);
/* OCRAM memory */
memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
&err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram",
FSL_IMX6_OCRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,

7
hw/arm/integratorcp.c
View file

@ -291,12 +291,9 @@ static void integratorcm_realize(DeviceState *d, Error **errp)
{
IntegratorCMState *s = INTEGRATOR_CM(d);
SysBusDevice *dev = SYS_BUS_DEVICE(d);
Error *local_err = NULL;
memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash",
0x100000, errp)) {
return;
}

26
hw/arm/mps2-tz.c
View file

@ -813,12 +813,6 @@ static void mps2tz_common_init(MachineState *machine)
int num_ppcs;
int i;
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
mc->default_cpu_type);
exit(1);
}
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
error_report("Invalid RAM size, should be %s", sz);
@ -1318,6 +1312,10 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m33"),
NULL
};
mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
mc->default_cpus = 1;
@ -1325,6 +1323,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN505;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045050;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@ -1347,6 +1346,10 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m33"),
NULL
};
mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
mc->default_cpus = 2;
@ -1354,6 +1357,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN521;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045210;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@ -1376,6 +1380,10 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m33"),
NULL
};
mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
mc->default_cpus = 2;
@ -1383,6 +1391,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN524;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045240;
mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@ -1410,6 +1419,10 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m55"),
NULL
};
mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55";
mc->default_cpus = 1;
@ -1417,6 +1430,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN547;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41055470;
mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */

26
hw/arm/mps2.c
View file

@ -142,12 +142,6 @@ static void mps2_common_init(MachineState *machine)
QList *oscclk;
int i;
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
mc->default_cpu_type);
exit(1);
}
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
error_report("Invalid RAM size, should be %s", sz);
@ -484,10 +478,15 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
};
mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN385;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41043850;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;
@ -498,10 +497,15 @@ static void mps2_an386_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
};
mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
mmc->fpga_type = FPGA_AN386;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41043860;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;
@ -512,10 +516,15 @@ static void mps2_an500_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m7"),
NULL
};
mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
mmc->fpga_type = FPGA_AN500;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045000;
mmc->psram_base = 0x60000000;
mmc->ethernet_base = 0xa0000000;
@ -526,10 +535,15 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
};
mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN511;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045110;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;

12
hw/arm/msf2-som.c
View file

@ -55,12 +55,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
MemoryRegion *ddr = g_new(MemoryRegion, 1);
Clock *m3clk;
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
mc->default_cpu_type);
exit(1);
}
memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
&error_fatal);
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
@ -106,9 +100,15 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
static void emcraft_sf2_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m3"),
NULL
};
mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
mc->init = emcraft_sf2_s2s010_init;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)

12
hw/arm/musca.c
View file

@ -355,7 +355,6 @@ static void musca_init(MachineState *machine)
{
MuscaMachineState *mms = MUSCA_MACHINE(machine);
MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *system_memory = get_system_memory();
DeviceState *ssedev;
DeviceState *dev_splitter;
@ -366,12 +365,6 @@ static void musca_init(MachineState *machine)
assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
mc->default_cpu_type);
exit(1);
}
mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(mms->sysclk, SYSCLK_FRQ);
mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
@ -604,11 +597,16 @@ static void musca_init(MachineState *machine)
static void musca_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m33"),
NULL
};
mc->default_cpus = 2;
mc->min_cpus = mc->default_cpus;
mc->max_cpus = mc->default_cpus;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mc->valid_cpu_types = valid_cpu_types;
mc->init = musca_init;
}

12
hw/arm/npcm7xx_boards.c
View file

@ -121,15 +121,8 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
uint32_t hw_straps)
{
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
MachineClass *mc = MACHINE_CLASS(nmc);
Object *obj;
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with %s",
mc->default_cpu_type);
exit(1);
}
obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
&error_abort, NULL);
object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
@ -463,12 +456,17 @@ static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a9"),
NULL
};
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_parallel = 1;
mc->default_ram_id = "ram";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
mc->valid_cpu_types = valid_cpu_types;
}
/*

7
hw/arm/nrf51_soc.c
View file

@ -58,7 +58,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
NRF51State *s = NRF51_SOC(dev_soc);
MemoryRegion *mr;
Error *err = NULL;
uint8_t i = 0;
hwaddr base_addr = 0;
@ -92,10 +91,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
&err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
errp)) {
return;
}
memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);

12
hw/arm/orangepi.c
View file

@ -49,12 +49,6 @@ static void orangepi_init(MachineState *machine)
exit(1);
}
/* Only allow Cortex-A7 for this board */
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
error_report("This board can only be used with cortex-a7 CPU");
exit(1);
}
h3 = AW_H3(object_new(TYPE_AW_H3));
object_property_add_child(OBJECT(machine), "soc", OBJECT(h3));
object_unref(OBJECT(h3));
@ -111,6 +105,11 @@ static void orangepi_init(MachineState *machine)
static void orangepi_machine_init(MachineClass *mc)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
NULL
};
mc->desc = "Orange Pi PC (Cortex-A7)";
mc->init = orangepi_init;
mc->block_default_type = IF_SD;
@ -119,6 +118,7 @@ static void orangepi_machine_init(MachineClass *mc)
mc->max_cpus = AW_H3_NUM_CPUS;
mc->default_cpus = AW_H3_NUM_CPUS;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "orangepi.ram";
}

36
hw/arm/sbsa-ref.c
View file

@ -145,27 +145,6 @@ static const int sbsa_ref_irqmap[] = {
[SBSA_GWDT_WS0] = 16,
};
static const char * const valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
ARM_CPU_TYPE_NAME("neoverse-v1"),
ARM_CPU_TYPE_NAME("neoverse-n2"),
ARM_CPU_TYPE_NAME("max"),
};
static bool cpu_type_valid(const char *cpu)
{
int i;
for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
if (strcmp(cpu, valid_cpus[i]) == 0) {
return true;
}
}
return false;
}
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
{
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
@ -733,11 +712,6 @@ static void sbsa_ref_init(MachineState *machine)
const CPUArchIdList *possible_cpus;
int n, sbsa_max_cpus;
if (!cpu_type_valid(machine->cpu_type)) {
error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type);
exit(1);
}
if (kvm_enabled()) {
error_report("sbsa-ref: KVM is not supported for this machine");
exit(1);
@ -898,10 +872,20 @@ static void sbsa_ref_instance_init(Object *obj)
static void sbsa_ref_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
ARM_CPU_TYPE_NAME("neoverse-v1"),
ARM_CPU_TYPE_NAME("neoverse-n2"),
ARM_CPU_TYPE_NAME("max"),
NULL,
};
mc->init = sbsa_ref_init;
mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
mc->valid_cpu_types = valid_cpu_types;
mc->max_cpus = 512;
mc->pci_allow_0_address = true;
mc->minimum_page_bits = 12;

60
hw/arm/virt.c
View file

@ -204,38 +204,6 @@ static const int a15irqmap[] = {
[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
};
static const char *valid_cpus[] = {
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("cortex-a710"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
ARM_CPU_TYPE_NAME("neoverse-v1"),
ARM_CPU_TYPE_NAME("neoverse-n2"),
#endif
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
};
static bool cpu_type_valid(const char *cpu)
{
int i;
for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
if (strcmp(cpu, valid_cpus[i]) == 0) {
return true;
}
}
return false;
}
static void create_randomness(MachineState *ms, const char *node)
{
struct {
@ -2040,11 +2008,6 @@ static void machvirt_init(MachineState *machine)
unsigned int smp_cpus = machine->smp.cpus;
unsigned int max_cpus = machine->smp.max_cpus;
if (!cpu_type_valid(machine->cpu_type)) {
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
exit(1);
}
possible_cpus = mc->possible_cpu_arch_ids(machine);
/*
@ -2938,6 +2901,28 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
static const char * const valid_cpu_types[] = {
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("cortex-a710"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
ARM_CPU_TYPE_NAME("neoverse-v1"),
ARM_CPU_TYPE_NAME("neoverse-n2"),
#endif
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
ARM_CPU_TYPE_NAME("host"),
#endif
ARM_CPU_TYPE_NAME("max"),
NULL
};
mc->init = machvirt_init;
/* Start with max_cpus set to 512, which is the maximum supported by KVM.
@ -2964,6 +2949,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
#else
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
#endif
mc->valid_cpu_types = valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
assert(!mc->get_hotplug_handler);

10
hw/audio/sb16.c
View file

@ -1325,11 +1325,11 @@ static const VMStateDescription vmstate_sb16 = {
.minimum_version_id = 1,
.post_load = sb16_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINT32 (irq, SB16State),
VMSTATE_UINT32 (dma, SB16State),
VMSTATE_UINT32 (hdma, SB16State),
VMSTATE_UINT32 (port, SB16State),
VMSTATE_UINT32 (ver, SB16State),
VMSTATE_UNUSED( 4 /* irq */
+ 4 /* dma */
+ 4 /* hdma */
+ 4 /* port */
+ 4 /* ver */),
VMSTATE_INT32 (in_index, SB16State),
VMSTATE_INT32 (out_data_len, SB16State),
VMSTATE_INT32 (fmt_stereo, SB16State),

8
hw/core/cpu-common.c
View file

@ -154,10 +154,12 @@ ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
assert(cc->class_by_name);
assert(cpu_model);
oc = cc->class_by_name(cpu_model);
if (oc == NULL || object_class_is_abstract(oc)) {
return NULL;
if (object_class_dynamic_cast(oc, typename) &&
!object_class_is_abstract(oc)) {
return oc;
}
return oc;
return NULL;
}
static void cpu_common_parse_features(const char *typename, char *features,

103
hw/core/machine.c
View file

@ -1390,13 +1390,74 @@ out:
return r;
}
const char *machine_class_default_cpu_type(MachineClass *mc)
{
if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) {
/* Only a single CPU type allowed: use it as default. */
return mc->valid_cpu_types[0];
}
return mc->default_cpu_type;
}
static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
ObjectClass *oc = object_class_by_name(machine->cpu_type);
CPUClass *cc;
int i;
/*
* Check if the user specified CPU type is supported when the valid
* CPU types have been determined. Note that the user specified CPU
* type is provided through '-cpu' option.
*/
if (mc->valid_cpu_types) {
assert(mc->valid_cpu_types[0] != NULL);
for (i = 0; mc->valid_cpu_types[i]; i++) {
if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) {
break;
}
}
/* The user specified CPU type isn't valid */
if (!mc->valid_cpu_types[i]) {
g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
error_setg(errp, "Invalid CPU model: %s", requested);
if (!mc->valid_cpu_types[1]) {
g_autofree char *model = cpu_model_from_type(
mc->valid_cpu_types[0]);
error_append_hint(errp, "The only valid type is: %s\n", model);
} else {
error_append_hint(errp, "The valid models are: ");
for (i = 0; mc->valid_cpu_types[i]; i++) {
g_autofree char *model = cpu_model_from_type(
mc->valid_cpu_types[i]);
error_append_hint(errp, "%s%s",
model,
mc->valid_cpu_types[i + 1] ? ", " : "");
}
error_append_hint(errp, "\n");
}
return false;
}
}
/* Check if CPU type is deprecated and warn if so */
cc = CPU_CLASS(oc);
assert(cc != NULL);
if (cc->deprecation_note) {
warn_report("CPU model %s is deprecated -- %s",
machine->cpu_type, cc->deprecation_note);
}
return true;
}
void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
{
ERRP_GUARD();
MachineClass *machine_class = MACHINE_GET_CLASS(machine);
ObjectClass *oc = object_class_by_name(machine->cpu_type);
CPUClass *cc;
/* This checkpoint is required by replay to separate prior clock
reading from the other reads, because timer polling functions query
@ -1451,41 +1512,9 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error *
machine->ram = machine_consume_memdev(machine, machine->memdev);
}
/* If the machine supports the valid_cpu_types check and the user
* specified a CPU with -cpu check here that the user CPU is supported.
*/
if (machine_class->valid_cpu_types && machine->cpu_type) {
int i;
for (i = 0; machine_class->valid_cpu_types[i]; i++) {
if (object_class_dynamic_cast(oc,
machine_class->valid_cpu_types[i])) {
/* The user specified CPU is in the valid field, we are
* good to go.
*/
break;
}
}
if (!machine_class->valid_cpu_types[i]) {
/* The user specified CPU is not valid */
error_report("Invalid CPU type: %s", machine->cpu_type);
error_printf("The valid types are: %s",
machine_class->valid_cpu_types[0]);
for (i = 1; machine_class->valid_cpu_types[i]; i++) {
error_printf(", %s", machine_class->valid_cpu_types[i]);
}
error_printf("\n");
exit(1);
}
}
/* Check if CPU type is deprecated and warn if so */
cc = CPU_CLASS(oc);
if (cc && cc->deprecation_note) {
warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
cc->deprecation_note);
/* Check if the CPU type is supported */
if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) {
return;
}
if (machine->cgs) {

5
hw/cpu/cluster.c
View file

@ -19,12 +19,11 @@
*/
#include "qemu/osdep.h"
#include "hw/core/cpu.h"
#include "hw/cpu/cluster.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/cutils.h"
static Property cpu_cluster_properties[] = {
DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0),

9
hw/cpu/core.c
View file

@ -8,12 +8,11 @@
*/
#include "qemu/osdep.h"
#include "hw/cpu/core.h"
#include "qapi/visitor.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
#include "hw/boards.h"
#include "hw/cpu/core.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
static void core_prop_get_core_id(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)

20
hw/m68k/mcf5206.c
View file

@ -148,15 +148,11 @@ static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
m5206_timer_update(s);
}
static m5206_timer_state *m5206_timer_init(qemu_irq irq)
static void m5206_timer_init(m5206_timer_state *s, qemu_irq irq)
{
m5206_timer_state *s;
s = g_new0(m5206_timer_state, 1);
s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_LEGACY);
s->irq = irq;
m5206_timer_reset(s);
return s;
}
/* System Integration Module. */
@ -167,7 +163,7 @@ typedef struct {
M68kCPU *cpu;
MemoryRegion iomem;
qemu_irq *pic;
m5206_timer_state *timer[2];
m5206_timer_state timer[2];
DeviceState *uart[2];
uint8_t scr;
uint8_t icr[14];
@ -293,9 +289,9 @@ static uint64_t m5206_mbar_read(m5206_mbar_state *s,
uint16_t offset, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
return m5206_timer_read(s->timer[0], offset - 0x100);
return m5206_timer_read(&s->timer[0], offset - 0x100);
} else if (offset >= 0x120 && offset < 0x140) {
return m5206_timer_read(s->timer[1], offset - 0x120);
return m5206_timer_read(&s->timer[1], offset - 0x120);
} else if (offset >= 0x140 && offset < 0x160) {
return mcf_uart_read(s->uart[0], offset - 0x140, size);
} else if (offset >= 0x180 && offset < 0x1a0) {
@ -333,10 +329,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint16_t offset,
uint64_t value, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
m5206_timer_write(s->timer[0], offset - 0x100, value);
m5206_timer_write(&s->timer[0], offset - 0x100, value);
return;
} else if (offset >= 0x120 && offset < 0x140) {
m5206_timer_write(s->timer[1], offset - 0x120, value);
m5206_timer_write(&s->timer[1], offset - 0x120, value);
return;
} else if (offset >= 0x140 && offset < 0x160) {
mcf_uart_write(s->uart[0], offset - 0x140, value, size);
@ -598,8 +594,8 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
s->pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
s->timer[0] = m5206_timer_init(s->pic[9]);
s->timer[1] = m5206_timer_init(s->pic[10]);
m5206_timer_init(&s->timer[0], s->pic[9]);
m5206_timer_init(&s->timer[1], s->pic[10]);
s->uart[0] = mcf_uart_create(s->pic[12], serial_hd(0));
s->uart[1] = mcf_uart_create(s->pic[13], serial_hd(1));
}

7
hw/mips/cps.c
View file

@ -78,10 +78,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
CPUMIPSState *env = &cpu->env;
/* All VPs are halted on reset. Leave powering up to CPC. */
if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
errp)) {
return;
}
object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
&error_abort);
/* All cores use the same clock tree */
qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);

10
hw/mips/jazz.c
View file

@ -36,7 +36,6 @@
#include "hw/boards.h"
#include "net/net.h"
#include "hw/scsi/esp.h"
#include "hw/mips/bios.h"
#include "hw/loader.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/timer/i8254.h"
@ -53,12 +52,19 @@
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#endif /* CONFIG_TCG */
#include "cpu.h"
enum jazz_model_e {
JAZZ_MAGNUM,
JAZZ_PICA61,
};
#if TARGET_BIG_ENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
#define BIOS_FILENAME "mipsel_bios.bin"
#endif
static void main_cpu_reset(void *opaque)
{
MIPSCPU *cpu = opaque;
@ -147,6 +153,8 @@ static void mips_jazz_init_net(NICInfo *nd, IOMMUMemoryRegion *rc4030_dma_mr,
prom[7] = 0xff - checksum;
}
#define BIOS_SIZE (4 * MiB)
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

9
hw/mips/malta.c
View file

@ -40,7 +40,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "hw/loader.h"
@ -59,6 +58,7 @@
#include "hw/qdev-clock.h"
#include "target/mips/internal.h"
#include "trace.h"
#include "cpu.h"
#define ENVP_PADDR 0x2000
#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
@ -71,6 +71,7 @@
#define RESET_ADDRESS 0x1fc00000ULL
#define FLASH_SIZE 0x400000
#define BIOS_SIZE (4 * MiB)
#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
@ -91,6 +92,12 @@ typedef struct {
bool display_inited;
} MaltaFPGAState;
#if TARGET_BIG_ENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
#define BIOS_FILENAME "mipsel_bios.bin"
#endif
#define TYPE_MIPS_MALTA "mips-malta"
OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)

10
hw/mips/mipssim.c
View file

@ -35,7 +35,6 @@
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/mips/bios.h"
#include "hw/loader.h"
#include "elf.h"
#include "hw/sysbus.h"
@ -43,6 +42,15 @@
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "cpu.h"
#define BIOS_SIZE (4 * MiB)
#if TARGET_BIG_ENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
#define BIOS_FILENAME "mipsel_bios.bin"
#endif
static struct _loaderparams {
int ram_size;

8
hw/misc/ivshmem.c
View file

@ -476,7 +476,6 @@ static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
{
Error *local_err = NULL;
struct stat buf;
size_t size;
@ -496,10 +495,9 @@ static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
size = buf.st_size;
/* mmap the region and map into the BAR2 */
memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s), "ivshmem.bar2",
size, RAM_SHARED, fd, 0, &local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s),
"ivshmem.bar2", size, RAM_SHARED,
fd, 0, errp)) {
return;
}

2
hw/net/can/can_sja1000.c
View file

@ -108,7 +108,7 @@ void can_sja_single_filter(struct qemu_can_filter *filter,
}
filter->can_mask = (uint32_t)amr[0] << 3;
filter->can_mask |= (uint32_t)amr[1] << 5;
filter->can_mask |= (uint32_t)amr[1] >> 5;
filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK;
if (!(amr[1] & 0x10)) {
filter->can_mask |= QEMU_CAN_RTR_FLAG;

7
hw/nvram/nrf51_nvm.c
View file

@ -336,12 +336,9 @@ static void nrf51_nvm_init(Object *obj)
static void nrf51_nvm_realize(DeviceState *dev, Error **errp)
{
NRF51NVMState *s = NRF51_NVM(dev);
Error *err = NULL;
memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s,
"nrf51_soc.flash", s->flash_size, &err);
if (err) {
error_propagate(errp, err);
if (!memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s,
"nrf51_soc.flash", s->flash_size, errp)) {
return;
}

6
hw/pci-host/raven.c
View file

@ -345,8 +345,10 @@ static void raven_realize(PCIDevice *d, Error **errp)
d->config[PCI_LATENCY_TIMER] = 0x10;
d->config[PCI_CAPABILITY_LIST] = 0x00;
memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
&error_fatal);
if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios",
BIOS_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
&s->bios);
if (s->bios_name) {

2
hw/ppc/e500.c
View file

@ -955,7 +955,7 @@ void ppce500_init(MachineState *machine)
* when implementing non-kernel boot.
*/
object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
&error_fatal);
&error_abort);
qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
if (!firstenv) {

7
hw/ppc/rs6000_mc.c
View file

@ -143,7 +143,6 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
RS6000MCState *s = RS6000MC(dev);
int socket = 0;
unsigned int ram_size = s->ram_size / MiB;
Error *local_err = NULL;
while (socket < 6) {
if (ram_size >= 64) {
@ -165,10 +164,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
if (s->simm_size[socket]) {
char name[] = "simm.?";
name[5] = socket + '0';
memory_region_init_ram(&s->simm[socket], OBJECT(dev), name,
s->simm_size[socket] * MiB, &local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram(&s->simm[socket], OBJECT(dev), name,
s->simm_size[socket] * MiB, errp)) {
return;
}
memory_region_add_subregion_overlap(get_system_memory(), 0,

2
hw/ppc/spapr_cpu_core.c
View file

@ -306,7 +306,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
* All CPUs start halted. CPU0 is unhalted from the machine level reset code
* and the rest are explicitly started up by the guest using an RTAS call.
*/
cs->start_powered_off = true;
qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true);
cs->cpu_index = cc->core_id + i;
if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
return NULL;

13
hw/riscv/shakti_c.c
View file

@ -28,7 +28,6 @@
#include "exec/address-spaces.h"
#include "hw/riscv/boot.h"
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@ -47,12 +46,6 @@ static void shakti_c_machine_state_init(MachineState *mstate)
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
/* Allow only Shakti C CPU for this platform */
if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
error_report("This board can only be used with Shakti C CPU");
exit(1);
}
/* Initialize SoC */
object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
TYPE_RISCV_SHAKTI_SOC);
@ -82,9 +75,15 @@ static void shakti_c_machine_instance_init(Object *obj)
static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
{
MachineClass *mc = MACHINE_CLASS(klass);
static const char * const valid_cpu_types[] = {
RISCV_CPU_TYPE_NAME("shakti-c"),
NULL
};
mc->desc = "RISC-V Board compatible with Shakti SDK";
mc->init = shakti_c_machine_state_init;
mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "riscv.shakti.c.ram";
}

8
hw/sparc/leon3.c
View file

@ -164,9 +164,9 @@ static void leon3_cache_control_int(CPUSPARCState *env)
}
}
static void leon3_irq_ack(void *irq_manager, int intno)
static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
grlib_irqmp_ack((DeviceState *)irq_manager, intno);
grlib_irqmp_ack(env->irq_manager, intno);
}
/*
@ -208,9 +208,9 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
}
}
static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
static void leon3_irq_manager(CPUSPARCState *env, int intno)
{
leon3_irq_ack(irq_manager, intno);
leon3_irq_ack(env, intno);
leon3_cache_control_int(env);
}

23
hw/sparc/sun4m.c
View file

@ -577,12 +577,9 @@ static void idreg_realize(DeviceState *ds, Error **errp)
{
IDRegState *s = MACIO_ID_REGISTER(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
Error *local_err = NULL;
memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
sizeof(idreg_data), &local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
sizeof(idreg_data), errp)) {
return;
}
@ -631,12 +628,9 @@ static void afx_realize(DeviceState *ds, Error **errp)
{
AFXState *s = TCX_AFX(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
Error *local_err = NULL;
memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx",
4, errp)) {
return;
}
@ -715,12 +709,9 @@ static void prom_realize(DeviceState *ds, Error **errp)
{
PROMState *s = OPENPROM(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
Error *local_err = NULL;
memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
PROM_SIZE_MAX, &local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
PROM_SIZE_MAX, errp)) {
return;
}
@ -804,7 +795,7 @@ static void cpu_devinit(const char *cpu_type, unsigned int id,
qemu_register_reset(sun4m_cpu_reset, cpu);
object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
&error_fatal);
&error_abort);
qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
cpu_sparc_set_id(env, id);
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);

7
hw/sparc64/sun4u.c
View file

@ -454,12 +454,9 @@ static void prom_realize(DeviceState *ds, Error **errp)
{
PROMState *s = OPENPROM(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
Error *local_err = NULL;
memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
PROM_SIZE_MAX, &local_err);
if (local_err) {
error_propagate(errp, local_err);
if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
PROM_SIZE_MAX, errp)) {
return;
}

6
hw/virtio/virtio-mem.c
View file

@ -605,8 +605,7 @@ static int virtio_mem_set_block_state(VirtIOMEM *vmem, uint64_t start_gpa,
int fd = memory_region_get_fd(&vmem->memdev->mr);
Error *local_err = NULL;
qemu_prealloc_mem(fd, area, size, 1, NULL, &local_err);
if (local_err) {
if (!qemu_prealloc_mem(fd, area, size, 1, NULL, &local_err)) {
static bool warned;
/*
@ -1249,8 +1248,7 @@ static int virtio_mem_prealloc_range_cb(VirtIOMEM *vmem, void *arg,
int fd = memory_region_get_fd(&vmem->memdev->mr);
Error *local_err = NULL;
qemu_prealloc_mem(fd, area, size, 1, NULL, &local_err);
if (local_err) {
if (!qemu_prealloc_mem(fd, area, size, 1, NULL, &local_err)) {
error_report_err(local_err);
return -ENOMEM;
}