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ppc/pnv: Add initial P9/10 SBE model

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The SBE (Self Boot Engine) are on-chip microcontrollers that perform
early boot steps, as well as provide some runtime facilities (e.g.,
timer, secure register access, MPIPL). The latter facilities are
accessed mostly via a message system called SBEFIFO.

This driver provides initial emulation for the SBE runtime registers
and a very basic SBEFIFO implementation that provides the timer
command. This covers the basic SBE behaviour expected by skiboot when
booting.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220811093726.1442343-1-npiggin@gmail.com>
[danielhb: fixed SBE_HOST_RESPONSE_MASK long line]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Nicholas Piggin 2022-08-11 19:37:26 +10:00 • committed by Daniel Henrique Barboza
parent 21d3a78ed9
commit 0bf4d77e59
8 changed files with 524 additions and 0 deletions
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25
hw/ppc/pnv.c
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@ -1397,6 +1397,8 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
/* Number of PECs is the chip default */
@ -1549,6 +1551,17 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
&chip9->occ.sram_regs);
/* SBE */
if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
&chip9->sbe.xscom_ctrl_regs);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
&chip9->sbe.xscom_mbox_regs);
qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
/* HOMER */
object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
&error_abort);
@ -1613,6 +1626,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
chip->num_pecs = pcc->num_pecs;
@ -1754,6 +1768,17 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
PNV10_OCC_SENSOR_BASE(chip),
&chip10->occ.sram_regs);
/* SBE */
if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
&chip10->sbe.xscom_ctrl_regs);
pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
&chip10->sbe.xscom_mbox_regs);
qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
/* HOMER */
object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
&error_abort);