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hw/misc/aspeed_hace: Extract SG-mode hash buffer setup into helper function
To improve code readability and maintainability of do_hash_operation(), this commit introduces a new helper function: hash_prepare_sg_iov(). This function handles scatter-gather (SG) mode setup, including SG list parsing, address mapping, and optional accumulation mode support with padding detection. No functional changes are introduced. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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parent
7328c48b57
commit
0b7dd5f991
1 changed files with 63 additions and 48 deletions
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@ -167,6 +167,67 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov)
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return iov_idx;
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}
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static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov,
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bool acc_mode, bool *acc_final_request)
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{
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uint32_t total_msg_len;
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uint32_t pad_offset;
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uint32_t len = 0;
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uint32_t sg_addr;
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uint32_t src;
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int iov_idx;
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hwaddr plen;
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void *haddr;
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for (iov_idx = 0; !(len & SG_LIST_LEN_LAST); iov_idx++) {
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if (iov_idx == ASPEED_HACE_MAX_SG) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Failed to set end of sg list marker\n",
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__func__);
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return -1;
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}
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src = s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE);
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len = address_space_ldl_le(&s->dram_as, src,
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MEMTXATTRS_UNSPECIFIED, NULL);
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sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
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MEMTXATTRS_UNSPECIFIED, NULL);
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sg_addr &= SG_LIST_ADDR_MASK;
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plen = len & SG_LIST_LEN_MASK;
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haddr = address_space_map(&s->dram_as, sg_addr, &plen, false,
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MEMTXATTRS_UNSPECIFIED);
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if (haddr == NULL) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unable to map address, sg_addr=0x%x, "
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"plen=0x%" HWADDR_PRIx "\n",
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__func__, sg_addr, plen);
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return -1;
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}
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iov[iov_idx].iov_base = haddr;
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if (acc_mode) {
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s->total_req_len += plen;
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if (has_padding(s, &iov[iov_idx], plen, &total_msg_len,
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&pad_offset)) {
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/* Padding being present indicates the final request */
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*acc_final_request = true;
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iov[iov_idx].iov_len = pad_offset;
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} else {
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iov[iov_idx].iov_len = plen;
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}
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} else {
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iov[iov_idx].iov_len = plen;
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}
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}
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return iov_idx;
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}
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static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
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bool acc_mode)
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{
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@ -174,15 +235,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
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struct iovec iov[ASPEED_HACE_MAX_SG];
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bool acc_final_request = false;
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Error *local_err = NULL;
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uint32_t total_msg_len;
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size_t digest_len = 0;
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uint32_t sg_addr = 0;
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uint32_t pad_offset;
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int iov_idx = 0;
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uint32_t len = 0;
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uint32_t src = 0;
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void *haddr;
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hwaddr plen;
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int iov_idx = -1;
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if (acc_mode && s->hash_ctx == NULL) {
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s->hash_ctx = qcrypto_hash_new(algo, &local_err);
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@ -196,46 +250,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
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/* Prepares the iov for hashing operations based on the selected mode */
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if (sg_mode) {
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for (iov_idx = 0; !(len & SG_LIST_LEN_LAST); iov_idx++) {
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if (iov_idx == ASPEED_HACE_MAX_SG) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"aspeed_hace: guest failed to set end of sg list marker\n");
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break;
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}
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src = s->regs[R_HASH_SRC] + (iov_idx * SG_LIST_ENTRY_SIZE);
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len = address_space_ldl_le(&s->dram_as, src,
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MEMTXATTRS_UNSPECIFIED, NULL);
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sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
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MEMTXATTRS_UNSPECIFIED, NULL);
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sg_addr &= SG_LIST_ADDR_MASK;
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plen = len & SG_LIST_LEN_MASK;
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haddr = address_space_map(&s->dram_as, sg_addr, &plen, false,
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MEMTXATTRS_UNSPECIFIED);
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if (haddr == NULL) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: qcrypto failed\n", __func__);
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return;
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}
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iov[iov_idx].iov_base = haddr;
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if (acc_mode) {
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s->total_req_len += plen;
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if (has_padding(s, &iov[iov_idx], plen, &total_msg_len,
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&pad_offset)) {
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/* Padding being present indicates the final request */
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acc_final_request = true;
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iov[iov_idx].iov_len = pad_offset;
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} else {
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iov[iov_idx].iov_len = plen;
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}
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} else {
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iov[iov_idx].iov_len = plen;
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}
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}
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iov_idx = hash_prepare_sg_iov(s, iov, acc_mode, &acc_final_request);
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} else {
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iov_idx = hash_prepare_direct_iov(s, iov);
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}
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