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trivial-patches 25-07-2023

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial-patches 25-07-2023

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# gpg: Signature made Tue 25 Jul 2023 15:23:52 BST
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
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# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
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* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu:
  qapi: Correct "eg." to "e.g." in documentation
  hw/pci: add comment to explain checking for available function 0 in pci hotplug
  target/tricore: Rename tricore_feature
  hw/9pfs: spelling fixes
  other architectures: spelling fixes
  arm: spelling fixes
  s390x: spelling fixes
  migration: spelling fixes

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-07-25 16:30:51 +01:00
commit 0b58dc4561
78 changed files with 125 additions and 120 deletions
Download patch file Download diff file Expand all files Collapse all files

14
target/sparc/asi.h
View file

@ -144,13 +144,13 @@
* ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
* and later ASIs.
*/
#define ASI_REAL 0x14 /* Real address, cachable */
#define ASI_REAL 0x14 /* Real address, cacheable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
#define ASI_REAL_IO 0x15 /* Real address, non-cachable */
#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
#define ASI_REAL_L 0x1c /* Real address, cachable, LE */
#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */
#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
@ -163,15 +163,15 @@
#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
* secondary, user
*/
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */
#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */
#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */
#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
#define ASI_TWINX_N 0x27 /* twin load, nucleus */
#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */
#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */
#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */
#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */
#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
@ -231,7 +231,7 @@
#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */