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i386: Introduce SnowRidge CPU model

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SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.

MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access

References can be found in either:
 https://software.intel.com/en-us/articles/intel-sdm
 https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference

Signed-off-by: Paul Lai <paul.c.lai@intel.com>
Tested-by: Tao3 Xu <tao3.xu@intel.com>
Message-Id: <20190626162129.25345-1-paul.c.lai@intel.com>
[ehabkost: squashed SPLIT_LOCK_DETECT patch]
Message-Id: <20190626163232.25711-1-paul.c.lai@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Paul Lai 2019-06-26 09:21:29 -07:00 • committed by Eduardo Habkost
parent 79974027dc
commit 0b18874bd2
1 changed files with 71 additions and 0 deletions
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71
target/i386/cpu.c
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@ -2688,6 +2688,77 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008, .xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)", .model_id = "Intel Xeon Processor (Icelake)",
}, },
{
.name = "SnowRidge-Server",
.level = 27,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 134,
.stepping = 1,
.features[FEAT_1_EDX] =
/* missing: CPUID_PN CPUID_IA64 */
/* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
CPUID_CX8 | CPUID_APIC | CPUID_SEP |
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
CPUID_MMX |
CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
CPUID_EXT_VMX |
CPUID_EXT_SSSE3 |
CPUID_EXT_CX16 |
CPUID_EXT_SSE41 |
CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
CPUID_EXT_POPCNT |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_SYSCALL |
CPUID_EXT2_NX |
CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
CPUID_EXT2_LM,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM |
CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE |
CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS |
CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
CPUID_7_0_EBX_RDSEED |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_CLWB |
CPUID_7_0_EBX_SHA_NI,
.features[FEAT_7_0_ECX] =
CPUID_7_0_ECX_UMIP |
/* missing bit 5 */
CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
CPUID_7_0_ECX_MOVDIR64B,
.features[FEAT_7_0_EDX] =
CPUID_7_0_EDX_SPEC_CTRL |
CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
CPUID_7_0_EDX_CORE_CAPABILITY,
.features[FEAT_CORE_CAPABILITY] =
MSR_CORE_CAP_SPLIT_LOCK_DETECT,
/*
* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Atom Processor (SnowRidge)",
},
{ {
.name = "KnightsMill", .name = "KnightsMill",
.level = 0xd, .level = 0xd,