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ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

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Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <39e5129dd095b285676a6267c5753786da1bc30d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-09-24 14:27:55 +02:00 • committed by Daniel Henrique Barboza
parent 2cdfa6ef5c
commit 0aedcc8a8d
6 changed files with 10 additions and 39 deletions
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14
hw/ppc/ppc4xx_devs.c
View file

@ -41,7 +41,7 @@
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
@ -348,19 +348,17 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
Ppc4xxSdramBank *ram_banks)
MemoryRegion *ram)
{
ppc4xx_sdram_t *sdram;
int i;
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
sdram->bank[i].ram = ram_banks[i].ram;
sdram->bank[i].base = ram_banks[i].base;
sdram->bank[i].size = ram_banks[i].size;
}
ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);