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hw/misc: Store DRAM size in NPCM8XX GCR Module

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NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-9-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2025-02-19 10:45:59 -08:00 • committed by Peter Maydell
parent d9ffb75f2a
commit 0ad46bbb56
2 changed files with 25 additions and 0 deletions
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24
hw/misc/npcm_gcr.c
View file

@ -280,6 +280,19 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
}
static void npcm8xx_gcr_enter_reset(Object *obj, ResetType type)
{
NPCMGCRState *s = NPCM_GCR(obj);
NPCMGCRClass *c = NPCM_GCR_GET_CLASS(obj);
memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t));
/* These 3 registers are at the same location in both 7xx and 8xx. */
s->regs[NPCM8XX_GCR_PWRON] = s->reset_pwron;
s->regs[NPCM8XX_GCR_MDLR] = s->reset_mdlr;
s->regs[NPCM8XX_GCR_INTCR3] = s->reset_intcr3;
s->regs[NPCM8XX_GCR_SCRPAD_B] = s->reset_scrpad_b;
}
static void npcm_gcr_realize(DeviceState *dev, Error **errp)
{
ERRP_GUARD();
@ -323,6 +336,14 @@ static void npcm_gcr_realize(DeviceState *dev, Error **errp)
* https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
*/
s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
/*
* The boot block starting from 0.0.6 for NPCM8xx SoCs stores the DRAM size
* in the SCRPAD2 registers. We need to set this field correctly since
* the initialization is skipped as we mentioned above.
* https://github.com/Nuvoton-Israel/u-boot/blob/npcm8mnx-v2019.01_tmp/board/nuvoton/arbel/arbel.c#L737
*/
s->reset_scrpad_b = dram_size;
}
static void npcm_gcr_init(Object *obj)
@ -370,16 +391,19 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
c->nr_regs = NPCM7XX_GCR_NR_REGS;
c->cold_reset_values = npcm7xx_cold_reset_values;
rc->phases.enter = npcm7xx_gcr_enter_reset;
}
static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data)
{
NPCMGCRClass *c = NPCM_GCR_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "NPCM8xx System Global Control Registers";
c->nr_regs = NPCM8XX_GCR_NR_REGS;
c->cold_reset_values = npcm8xx_cold_reset_values;
rc->phases.enter = npcm8xx_gcr_enter_reset;
}
static const TypeInfo npcm_gcr_info[] = {

1
include/hw/misc/npcm_gcr.h
View file

@ -68,6 +68,7 @@ typedef struct NPCMGCRState {
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
uint32_t reset_scrpad_b;
} NPCMGCRState;
typedef struct NPCMGCRClass {