pull-loongarch-20230106

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Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20230106

# gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu:
  hw/intc/loongarch_pch: Change default irq number of pch irq controller
  hw/intc/loongarch_pch_pic: add irq number property
  hw/intc/loongarch_pch_msi: add irq number property

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-07 14:25:38 +00:00
commit 0ab12aa324
6 changed files with 77 additions and 23 deletions

View file

@ -32,7 +32,7 @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
*/ */
irq_num = (val & 0xff) - s->irq_base; irq_num = (val & 0xff) - s->irq_base;
trace_loongarch_msi_set_irq(irq_num); trace_loongarch_msi_set_irq(irq_num);
assert(irq_num < PCH_MSI_IRQ_NUM); assert(irq_num < s->irq_num);
qemu_set_irq(s->pch_msi_irq[irq_num], 1); qemu_set_irq(s->pch_msi_irq[irq_num], 1);
} }
@ -49,6 +49,28 @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
qemu_set_irq(s->pch_msi_irq[irq], level); qemu_set_irq(s->pch_msi_irq[irq], level);
} }
static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
error_setg(errp, "Invalid 'msi_irq_num'");
return;
}
s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
}
static void loongarch_pch_msi_unrealize(DeviceState *dev)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
g_free(s->pch_msi_irq);
}
static void loongarch_pch_msi_init(Object *obj) static void loongarch_pch_msi_init(Object *obj)
{ {
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj); LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
@ -59,12 +81,11 @@ static void loongarch_pch_msi_init(Object *obj)
sysbus_init_mmio(sbd, &s->msi_mmio); sysbus_init_mmio(sbd, &s->msi_mmio);
msi_nonbroken = true; msi_nonbroken = true;
qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
} }
static Property loongarch_msi_properties[] = { static Property loongarch_msi_properties[] = {
DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0), DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -72,6 +93,8 @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = loongarch_pch_msi_realize;
dc->unrealize = loongarch_pch_msi_unrealize;
device_class_set_props(dc, loongarch_msi_properties); device_class_set_props(dc, loongarch_msi_properties);
} }

View file

@ -6,12 +6,16 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/loongarch/virt.h" #include "hw/loongarch/virt.h"
#include "hw/pci-host/ls7a.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_pic.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "trace.h" #include "trace.h"
#include "qapi/error.h"
static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level) static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
{ {
@ -40,7 +44,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque); LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
uint64_t mask = 1ULL << irq; uint64_t mask = 1ULL << irq;
assert(irq < PCH_PIC_IRQ_NUM); assert(irq < s->irq_num);
trace_loongarch_pch_pic_irq_handler(irq, level); trace_loongarch_pch_pic_irq_handler(irq, level);
if (s->intedge & mask) { if (s->intedge & mask) {
@ -78,7 +82,12 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
val = PCH_PIC_INT_ID_VAL; val = PCH_PIC_INT_ID_VAL;
break; break;
case PCH_PIC_INT_ID_HI: case PCH_PIC_INT_ID_HI:
val = PCH_PIC_INT_ID_NUM; /*
* With 7A1000 manual
* bit 0-15 pch irqchip version
* bit 16-31 irq number supported with pch irqchip
*/
val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);
break; break;
case PCH_PIC_INT_MASK_LO: case PCH_PIC_INT_MASK_LO:
val = (uint32_t)s->int_mask; val = (uint32_t)s->int_mask;
@ -365,6 +374,19 @@ static void loongarch_pch_pic_reset(DeviceState *d)
s->int_polarity = 0x0; s->int_polarity = 0x0;
} }
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
{
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
error_setg(errp, "Invalid 'pic_irq_num'");
return;
}
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
}
static void loongarch_pch_pic_init(Object *obj) static void loongarch_pch_pic_init(Object *obj)
{ {
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj); LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
@ -382,10 +404,13 @@ static void loongarch_pch_pic_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem8); sysbus_init_mmio(sbd, &s->iomem8);
sysbus_init_mmio(sbd, &s->iomem32_high); sysbus_init_mmio(sbd, &s->iomem32_high);
qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
} }
static Property loongarch_pch_pic_properties[] = {
DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_loongarch_pch_pic = { static const VMStateDescription vmstate_loongarch_pch_pic = {
.name = TYPE_LOONGARCH_PCH_PIC, .name = TYPE_LOONGARCH_PCH_PIC,
.version_id = 1, .version_id = 1,
@ -411,8 +436,10 @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = loongarch_pch_pic_realize;
dc->reset = loongarch_pch_pic_reset; dc->reset = loongarch_pch_pic_reset;
dc->vmsd = &vmstate_loongarch_pch_pic; dc->vmsd = &vmstate_loongarch_pch_pic;
device_class_set_props(dc, loongarch_pch_pic_properties);
} }
static const TypeInfo loongarch_pch_pic_info = { static const TypeInfo loongarch_pch_pic_info = {

View file

@ -553,7 +553,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
LoongArchCPU *lacpu; LoongArchCPU *lacpu;
CPULoongArchState *env; CPULoongArchState *env;
CPUState *cpu_state; CPUState *cpu_state;
int cpu, pin, i; int cpu, pin, i, start, num;
ipi = qdev_new(TYPE_LOONGARCH_IPI); ipi = qdev_new(TYPE_LOONGARCH_IPI);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
@ -616,6 +616,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
} }
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
num = VIRT_PCH_PIC_IRQ_NUM;
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
d = SYS_BUS_DEVICE(pch_pic); d = SYS_BUS_DEVICE(pch_pic);
sysbus_realize_and_unref(d, &error_fatal); sysbus_realize_and_unref(d, &error_fatal);
memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
@ -627,20 +629,23 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
sysbus_mmio_get_region(d, 2)); sysbus_mmio_get_region(d, 2));
/* Connect 64 pch_pic irqs to extioi */ /* Connect pch_pic irqs to extioi */
for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) { for (int i = 0; i < num; i++) {
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
} }
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START); start = num;
num = EXTIOI_IRQS - start;
qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
d = SYS_BUS_DEVICE(pch_msi); d = SYS_BUS_DEVICE(pch_msi);
sysbus_realize_and_unref(d, &error_fatal); sysbus_realize_and_unref(d, &error_fatal);
sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
for (i = 0; i < PCH_MSI_IRQ_NUM; i++) { for (i = 0; i < num; i++) {
/* Connect 192 pch_msi irqs to extioi */ /* Connect pch_msi irqs to extioi */
qdev_connect_gpio_out(DEVICE(d), i, qdev_connect_gpio_out(DEVICE(d), i,
qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START)); qdev_get_gpio_in(extioi, i + start));
} }
loongarch_devices_init(pch_pic, lams); loongarch_devices_init(pch_pic, lams);

View file

@ -8,15 +8,16 @@
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
/* Msi irq start start from 64 to 255 */ /* MSI irq start from 32 to 255 */
#define PCH_MSI_IRQ_START 64 #define PCH_MSI_IRQ_START 32
#define PCH_MSI_IRQ_END 255 #define PCH_MSI_IRQ_END 255
#define PCH_MSI_IRQ_NUM 192 #define PCH_MSI_IRQ_NUM 224
struct LoongArchPCHMSI { struct LoongArchPCHMSI {
SysBusDevice parent_obj; SysBusDevice parent_obj;
qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM]; qemu_irq *pch_msi_irq;
MemoryRegion msi_mmio; MemoryRegion msi_mmio;
/* irq base passed to upper extioi intc */ /* irq base passed to upper extioi intc */
unsigned int irq_base; unsigned int irq_base;
unsigned int irq_num;
}; };

View file

@ -9,11 +9,8 @@
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
#define PCH_PIC_IRQ_START 0
#define PCH_PIC_IRQ_END 63
#define PCH_PIC_IRQ_NUM 64
#define PCH_PIC_INT_ID_VAL 0x7000000UL #define PCH_PIC_INT_ID_VAL 0x7000000UL
#define PCH_PIC_INT_ID_NUM 0x3f0001UL #define PCH_PIC_INT_ID_VER 0x1UL
#define PCH_PIC_INT_ID_LO 0x00 #define PCH_PIC_INT_ID_LO 0x00
#define PCH_PIC_INT_ID_HI 0x04 #define PCH_PIC_INT_ID_HI 0x04
@ -66,4 +63,5 @@ struct LoongArchPCHPIC {
MemoryRegion iomem32_low; MemoryRegion iomem32_low;
MemoryRegion iomem32_high; MemoryRegion iomem32_high;
MemoryRegion iomem8; MemoryRegion iomem8;
unsigned int irq_num;
}; };

View file

@ -32,9 +32,9 @@
* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
* used for pci device. * used for pci device.
*/ */
#define VIRT_PCH_PIC_IRQ_NUM 32
#define PCH_PIC_IRQ_OFFSET 64 #define PCH_PIC_IRQ_OFFSET 64
#define VIRT_DEVICE_IRQS 16 #define VIRT_DEVICE_IRQS 16
#define VIRT_PCI_IRQS 48
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) #define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
#define VIRT_UART_BASE 0x1fe001e0 #define VIRT_UART_BASE 0x1fe001e0
#define VIRT_UART_SIZE 0X100 #define VIRT_UART_SIZE 0X100