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target/riscv: Add Ssdbltrp CSRs handling

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Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-3-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Clément Léger 2025-01-10 13:54:33 +01:00 • committed by Alistair Francis
parent 507957eb2a
commit 0aadf8162a
5 changed files with 84 additions and 12 deletions
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17
target/riscv/cpu_helper.c
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@ -120,6 +120,19 @@ bool cpu_get_bcfien(CPURISCVState *env)
}
}
bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
{
#ifdef CONFIG_USER_ONLY
return false;
#else
if (virt) {
return (env->henvcfg & HENVCFG_DTE) != 0;
} else {
return (env->menvcfg & MENVCFG_DTE) != 0;
}
#endif
}
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)
{
@ -691,6 +704,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
g_assert(riscv_has_ext(env, RVH));
if (riscv_env_smode_dbltrp_enabled(env, current_virt)) {
mstatus_mask |= MSTATUS_SDT;
}
if (current_virt) {
/* Current V=1 and we are about to change to V=0 */
env->vsstatus = env->mstatus & mstatus_mask;