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target/mips: Introduce ase_3d_available() helper

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Determine if the MIPS-3D ASE is implemented by checking
the state of the 3D bit in the FIR CP1 control register.
Remove the then unused ASE_MIPS3D definition.

Note, this allows using MIPS-3D on the mips64dspr2 model.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241021145832.34920-1-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-10-21 11:33:19 -03:00
parent 74665884a5
commit 09968fc96c
5 changed files with 18 additions and 6 deletions
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4
target/mips/cpu-defs.c.inc
View file

@ -663,7 +663,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF, .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40, .SEGBITS = 40,
.PABITS = 36, .PABITS = 36,
.insn_flags = CPU_MIPS64R1 | ASE_MIPS3D, .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{ {
@ -692,7 +692,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF, .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42, .SEGBITS = 42,
.PABITS = 36, .PABITS = 36,
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, .insn_flags = CPU_MIPS64R2,
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{ {

6
target/mips/cpu.h
View file

@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
/* Check presence of MIPS-3D ASE */
static inline bool ase_3d_available(const CPUMIPSState *env)
{
return env->active_fpu.fcr0 & (1 << FCR0_3D);
}
/* Check presence of MSA implementation */ /* Check presence of MSA implementation */
static inline bool ase_msa_available(CPUMIPSState *env) static inline bool ase_msa_available(CPUMIPSState *env)
{ {

1
target/mips/mips-defs.h
View file

@ -26,7 +26,6 @@
* bits 24-39: MIPS ASEs * bits 24-39: MIPS ASEs
*/ */
#define ASE_MIPS16 0x0000000001000000ULL #define ASE_MIPS16 0x0000000001000000ULL
#define ASE_MIPS3D 0x0000000002000000ULL
#define ASE_MDMX 0x0000000004000000ULL #define ASE_MDMX 0x0000000004000000ULL
#define ASE_DSP 0x0000000008000000ULL #define ASE_DSP 0x0000000008000000ULL
#define ASE_DSP_R2 0x0000000010000000ULL #define ASE_DSP_R2 0x0000000010000000ULL

5
target/mips/tcg/micromips_translate.c.inc
View file

@ -2484,7 +2484,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_BC1TANY4; mips32_op = OPC_BC1TANY4;
do_cp1mips3d: do_cp1mips3d:
check_cop1x(ctx); check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D); if (!ase_3d_available(env)) {
gen_reserved_instruction(ctx);
break;
}
/* Fall through */ /* Fall through */
do_cp1branch: do_cp1branch:
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (env->CP0_Config1 & (1 << CP0C1_FP)) {

8
target/mips/tcg/translate.c
View file

@ -14710,7 +14710,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
} else { } else {
/* OPC_BC1ANY2 */ /* OPC_BC1ANY2 */
check_cop1x(ctx); check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D); if (!ase_3d_available(env)) {
return false;
}
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2); (rt >> 2) & 0x7, imm << 2);
} }
@ -14725,7 +14727,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cop1x(ctx); check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D); if (!ase_3d_available(env)) {
return false;
}
/* fall through */ /* fall through */
case OPC_BC1: case OPC_BC1:
check_cp1_enabled(ctx); check_cp1_enabled(ctx);