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target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2

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Starting with v7 of the debug architecture, there are three extra
ID registers that add information on top of that provided in
DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the
v7 debug architecture, DBGDEVID is optional, present only of
DBGDIDR.DEVID_imp is set. In v7.1 all three must be present.

Implement the missing registers.  Note that we only need to set the
values in the ARMISARegisters struct for the CPUs Cortex-A7, A15,
A53, A57 and A72 (plus the 32-bit 'max' which uses the Cortex-A53
values): earlier CPUs didn't implement v7 of the architecture, and
our other 64-bit CPUs (Cortex-A76, Neoverse-N1 and A64fx) don't have
AArch32 support at EL1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220630194116.3438513-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-06-30 20:41:15 +01:00
parent 40b200279c
commit 09754ca867
4 changed files with 55 additions and 0 deletions
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36
target/arm/debug_helper.c
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@ -999,6 +999,42 @@ void define_debug_regs(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &dbgdidr);
}
/*
* DBGDEVID is present in the v7 debug architecture if
* DBGDIDR.DEVID_imp is 1 (bit 15); from v7.1 and on it is
* mandatory (and bit 15 is RES1). DBGDEVID1 and DBGDEVID2 exist
* from v7.1 of the debug architecture. Because no fields have yet
* been defined in DBGDEVID2 (and quite possibly none will ever
* be) we don't define an ARMISARegisters field for it.
* These registers exist only if EL1 can use AArch32, but that
* happens naturally because they are only PL1 accessible anyway.
*/
if (extract32(cpu->isar.dbgdidr, 15, 1)) {
ARMCPRegInfo dbgdevid = {
.name = "DBGDEVID",
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 2, .crn = 7,
.access = PL1_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid,
};
define_one_arm_cp_reg(cpu, &dbgdevid);
}
if (cpu_isar_feature(aa32_debugv7p1, cpu)) {
ARMCPRegInfo dbgdevid12[] = {
{
.name = "DBGDEVID1",
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 1, .crn = 7,
.access = PL1_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1,
}, {
.name = "DBGDEVID2",
.cp = 14, .opc1 = 0, .crn = 7, .opc2 = 0, .crn = 7,
.access = PL1_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0,
},
};
define_arm_cp_regs(cpu, dbgdevid12);
}
brps = arm_num_brps(cpu);
wrps = arm_num_wrps(cpu);
ctx_cmps = arm_num_ctx_cmps(cpu);