mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 18:44:58 -06:00
disas/libvixl: Update to libvixl 1.4
Update our copy of libvixl to upstream's 1.4 release. Note that we no longer need any local fixes for compilation on 32 bit hosts -- they have all been integrated upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399040419-9227-1-git-send-email-peter.maydell@linaro.org Acked-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
cd2b9b8680
commit
09319b3041
11 changed files with 628 additions and 342 deletions
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@ -95,7 +95,7 @@ void Disassembler::VisitAddSubImmediate(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -142,7 +142,7 @@ void Disassembler::VisitAddSubShifted(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -180,7 +180,7 @@ void Disassembler::VisitAddSubExtended(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -215,7 +215,7 @@ void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -258,30 +258,30 @@ void Disassembler::VisitLogicalImmediate(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
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ASSERT((reg_size == kXRegSize) ||
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((reg_size == kWRegSize) && (value <= 0xffffffff)));
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VIXL_ASSERT((reg_size == kXRegSize) ||
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((reg_size == kWRegSize) && (value <= 0xffffffff)));
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// Test for movz: 16 bits set at positions 0, 16, 32 or 48.
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if (((value & 0xffffffffffff0000ULL) == 0ULL) ||
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((value & 0xffffffff0000ffffULL) == 0ULL) ||
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((value & 0xffff0000ffffffffULL) == 0ULL) ||
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((value & 0x0000ffffffffffffULL) == 0ULL)) {
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if (((value & UINT64_C(0xffffffffffff0000)) == 0) ||
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((value & UINT64_C(0xffffffff0000ffff)) == 0) ||
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((value & UINT64_C(0xffff0000ffffffff)) == 0) ||
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((value & UINT64_C(0x0000ffffffffffff)) == 0)) {
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return true;
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}
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// Test for movn: NOT(16 bits set at positions 0, 16, 32 or 48).
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if ((reg_size == kXRegSize) &&
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(((value & 0xffffffffffff0000ULL) == 0xffffffffffff0000ULL) ||
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((value & 0xffffffff0000ffffULL) == 0xffffffff0000ffffULL) ||
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((value & 0xffff0000ffffffffULL) == 0xffff0000ffffffffULL) ||
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((value & 0x0000ffffffffffffULL) == 0x0000ffffffffffffULL))) {
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(((~value & UINT64_C(0xffffffffffff0000)) == 0) ||
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((~value & UINT64_C(0xffffffff0000ffff)) == 0) ||
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((~value & UINT64_C(0xffff0000ffffffff)) == 0) ||
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((~value & UINT64_C(0x0000ffffffffffff)) == 0))) {
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return true;
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}
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if ((reg_size == kWRegSize) &&
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@ -337,7 +337,7 @@ void Disassembler::VisitLogicalShifted(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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@ -353,7 +353,7 @@ void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
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case CCMN_x: mnemonic = "ccmn"; break;
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case CCMP_w:
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case CCMP_x: mnemonic = "ccmp"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -368,7 +368,7 @@ void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
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case CCMN_x_imm: mnemonic = "ccmn"; break;
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case CCMP_w_imm:
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case CCMP_x_imm: mnemonic = "ccmp"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -421,7 +421,7 @@ void Disassembler::VisitConditionalSelect(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -520,7 +520,7 @@ void Disassembler::VisitExtract(Instruction* instr) {
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -538,7 +538,7 @@ void Disassembler::VisitPCRelAddressing(Instruction* instr) {
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void Disassembler::VisitConditionalBranch(Instruction* instr) {
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switch (instr->Mask(ConditionalBranchMask)) {
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case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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}
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@ -570,7 +570,7 @@ void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
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switch (instr->Mask(UnconditionalBranchMask)) {
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case B: mnemonic = "b"; break;
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case BL: mnemonic = "bl"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -591,7 +591,7 @@ void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
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FORMAT(CLS, "cls");
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#undef FORMAT
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case REV32_x: mnemonic = "rev32"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -690,7 +690,7 @@ void Disassembler::VisitDataProcessing3Source(Instruction* instr) {
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form = form_xxx;
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -705,7 +705,7 @@ void Disassembler::VisitCompareBranch(Instruction* instr) {
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case CBZ_x: mnemonic = "cbz"; break;
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case CBNZ_w:
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case CBNZ_x: mnemonic = "cbnz"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -722,7 +722,7 @@ void Disassembler::VisitTestBranch(Instruction* instr) {
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switch (instr->Mask(TestBranchMask)) {
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case TBZ: mnemonic = "tbz"; break;
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case TBNZ: mnemonic = "tbnz"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -742,7 +742,7 @@ void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
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case MOVZ_x: mnemonic = "movz"; break;
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case MOVK_w:
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case MOVK_x: mnemonic = "movk"; form = "'Rd, 'IMoveLSL"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -981,7 +981,7 @@ void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
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switch (instr->Mask(FPConditionalSelectMask)) {
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case FCSEL_s:
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case FCSEL_d: mnemonic = "fcsel"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -1033,7 +1033,7 @@ void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
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FORMAT(FMINNM, "fminnm");
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FORMAT(FNMUL, "fnmul");
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#undef FORMAT
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -1052,7 +1052,7 @@ void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
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FORMAT(FNMADD, "fnmadd");
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FORMAT(FNMSUB, "fnmsub");
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#undef FORMAT
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -1065,7 +1065,7 @@ void Disassembler::VisitFPImmediate(Instruction* instr) {
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switch (instr->Mask(FPImmediateMask)) {
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case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break;
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case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -1082,6 +1082,14 @@ void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
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case FMOV_xd: mnemonic = "fmov"; form = form_rf; break;
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case FMOV_sw:
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case FMOV_dx: mnemonic = "fmov"; form = form_fr; break;
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case FCVTAS_ws:
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case FCVTAS_xs:
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case FCVTAS_wd:
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case FCVTAS_xd: mnemonic = "fcvtas"; form = form_rf; break;
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case FCVTAU_ws:
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case FCVTAU_xs:
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case FCVTAU_wd:
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case FCVTAU_xd: mnemonic = "fcvtau"; form = form_rf; break;
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case FCVTMS_ws:
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case FCVTMS_xs:
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case FCVTMS_wd:
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@ -1141,7 +1149,7 @@ void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
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case UCVTF_sx_fixed:
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case UCVTF_dw_fixed:
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case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break;
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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Format(instr, mnemonic, form);
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}
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@ -1176,7 +1184,7 @@ void Disassembler::VisitSystem(Instruction* instr) {
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}
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}
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} else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
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ASSERT(instr->Mask(SystemHintMask) == HINT);
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VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT);
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switch (instr->ImmHint()) {
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case NOP: {
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mnemonic = "nop";
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@ -1184,6 +1192,24 @@ void Disassembler::VisitSystem(Instruction* instr) {
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break;
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}
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}
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} else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
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switch (instr->Mask(MemBarrierMask)) {
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case DMB: {
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mnemonic = "dmb";
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form = "'M";
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break;
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}
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case DSB: {
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mnemonic = "dsb";
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form = "'M";
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break;
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}
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case ISB: {
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mnemonic = "isb";
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form = NULL;
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break;
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}
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}
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}
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Format(instr, mnemonic, form);
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@ -1226,7 +1252,7 @@ void Disassembler::ProcessOutput(Instruction* /*instr*/) {
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void Disassembler::Format(Instruction* instr, const char* mnemonic,
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const char* format) {
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ASSERT(mnemonic != NULL);
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VIXL_ASSERT(mnemonic != NULL);
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ResetOutput();
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Substitute(instr, mnemonic);
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if (format != NULL) {
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@ -1268,8 +1294,9 @@ int Disassembler::SubstituteField(Instruction* instr, const char* format) {
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case 'A': return SubstitutePCRelAddressField(instr, format);
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case 'B': return SubstituteBranchTargetField(instr, format);
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case 'O': return SubstituteLSRegOffsetField(instr, format);
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case 'M': return SubstituteBarrierField(instr, format);
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default: {
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UNREACHABLE();
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VIXL_UNREACHABLE();
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return 1;
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}
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}
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@ -1294,7 +1321,7 @@ int Disassembler::SubstituteRegisterField(Instruction* instr,
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}
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break;
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}
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default: UNREACHABLE();
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default: VIXL_UNREACHABLE();
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}
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// Increase field length for registers tagged as stack.
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@ -1331,7 +1358,7 @@ int Disassembler::SubstituteRegisterField(Instruction* instr,
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int Disassembler::SubstituteImmediateField(Instruction* instr,
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const char* format) {
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ASSERT(format[0] == 'I');
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VIXL_ASSERT(format[0] == 'I');
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switch (format[1]) {
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case 'M': { // IMoveImm or IMoveLSL.
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@ -1339,10 +1366,10 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
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AppendToOutput("#0x%" PRIx64, imm);
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} else {
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ASSERT(format[5] == 'L');
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VIXL_ASSERT(format[5] == 'L');
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AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
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if (instr->ShiftMoveWide() > 0) {
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AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide());
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AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
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}
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}
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return 8;
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@ -1384,14 +1411,14 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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return 6;
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}
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case 'A': { // IAddSub.
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ASSERT(instr->ShiftAddSub() <= 1);
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VIXL_ASSERT(instr->ShiftAddSub() <= 1);
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int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
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AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
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return 7;
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}
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case 'F': { // IFPSingle, IFPDouble or IFPFBits.
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if (format[3] == 'F') { // IFPFbits.
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AppendToOutput("#%" PRId64, 64 - instr->FPScale());
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AppendToOutput("#%d", 64 - instr->FPScale());
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return 8;
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} else {
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AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
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@ -1412,27 +1439,27 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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return 5;
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}
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case 'P': { // IP - Conditional compare.
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AppendToOutput("#%" PRId64, instr->ImmCondCmp());
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AppendToOutput("#%d", instr->ImmCondCmp());
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return 2;
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}
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case 'B': { // Bitfields.
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return SubstituteBitfieldImmediateField(instr, format);
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}
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case 'E': { // IExtract.
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AppendToOutput("#%" PRId64, instr->ImmS());
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AppendToOutput("#%d", instr->ImmS());
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return 8;
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}
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case 'S': { // IS - Test and branch bit.
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AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) |
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instr->ImmTestBranchBit40());
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AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
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instr->ImmTestBranchBit40());
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return 2;
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}
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case 'D': { // IDebug - HLT and BRK instructions.
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AppendToOutput("#0x%" PRIx64, instr->ImmException());
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AppendToOutput("#0x%x", instr->ImmException());
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return 6;
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}
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default: {
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UNIMPLEMENTED();
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VIXL_UNIMPLEMENTED();
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return 0;
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}
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}
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@ -1441,7 +1468,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr,
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int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
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const char* format) {
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ASSERT((format[0] == 'I') && (format[1] == 'B'));
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VIXL_ASSERT((format[0] == 'I') && (format[1] == 'B'));
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unsigned r = instr->ImmR();
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unsigned s = instr->ImmS();
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@ -1455,19 +1482,19 @@ int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
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AppendToOutput("#%d", s + 1);
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return 5;
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} else {
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ASSERT(format[3] == '-');
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VIXL_ASSERT(format[3] == '-');
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AppendToOutput("#%d", s - r + 1);
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return 7;
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}
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}
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case 'Z': { // IBZ-r.
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ASSERT((format[3] == '-') && (format[4] == 'r'));
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VIXL_ASSERT((format[3] == '-') && (format[4] == 'r'));
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unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
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AppendToOutput("#%d", reg_size - r);
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return 5;
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}
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default: {
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UNREACHABLE();
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VIXL_UNREACHABLE();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -1476,7 +1503,7 @@ int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
|
|||
|
||||
int Disassembler::SubstituteLiteralField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(strncmp(format, "LValue", 6) == 0);
|
||||
VIXL_ASSERT(strncmp(format, "LValue", 6) == 0);
|
||||
USE(format);
|
||||
|
||||
switch (instr->Mask(LoadLiteralMask)) {
|
||||
|
|
@ -1484,7 +1511,7 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
|
|||
case LDR_x_lit:
|
||||
case LDR_s_lit:
|
||||
case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
|
||||
default: UNREACHABLE();
|
||||
default: VIXL_UNREACHABLE();
|
||||
}
|
||||
|
||||
return 6;
|
||||
|
|
@ -1492,12 +1519,12 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
|
|||
|
||||
|
||||
int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
||||
ASSERT(format[0] == 'H');
|
||||
ASSERT(instr->ShiftDP() <= 0x3);
|
||||
VIXL_ASSERT(format[0] == 'H');
|
||||
VIXL_ASSERT(instr->ShiftDP() <= 0x3);
|
||||
|
||||
switch (format[1]) {
|
||||
case 'D': { // HDP.
|
||||
ASSERT(instr->ShiftDP() != ROR);
|
||||
VIXL_ASSERT(instr->ShiftDP() != ROR);
|
||||
} // Fall through.
|
||||
case 'L': { // HLo.
|
||||
if (instr->ImmDPShift() != 0) {
|
||||
|
|
@ -1508,7 +1535,7 @@ int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
|||
return 3;
|
||||
}
|
||||
default:
|
||||
UNIMPLEMENTED();
|
||||
VIXL_UNIMPLEMENTED();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -1516,7 +1543,7 @@ int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
|
|||
|
||||
int Disassembler::SubstituteConditionField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(format[0] == 'C');
|
||||
VIXL_ASSERT(format[0] == 'C');
|
||||
const char* condition_code[] = { "eq", "ne", "hs", "lo",
|
||||
"mi", "pl", "vs", "vc",
|
||||
"hi", "ls", "ge", "lt",
|
||||
|
|
@ -1538,27 +1565,27 @@ int Disassembler::SubstituteConditionField(Instruction* instr,
|
|||
int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
|
||||
const char* format) {
|
||||
USE(format);
|
||||
ASSERT(strncmp(format, "AddrPCRel", 9) == 0);
|
||||
VIXL_ASSERT(strncmp(format, "AddrPCRel", 9) == 0);
|
||||
|
||||
int offset = instr->ImmPCRel();
|
||||
|
||||
// Only ADR (AddrPCRelByte) is supported.
|
||||
ASSERT(strcmp(format, "AddrPCRelByte") == 0);
|
||||
VIXL_ASSERT(strcmp(format, "AddrPCRelByte") == 0);
|
||||
|
||||
char sign = '+';
|
||||
if (offset < 0) {
|
||||
offset = -offset;
|
||||
sign = '-';
|
||||
}
|
||||
// TODO: Extend this to support printing the target address.
|
||||
AppendToOutput("#%c0x%x", sign, offset);
|
||||
VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
|
||||
AppendToOutput("#%c0x%x (addr %p)", sign, offset, instr + offset);
|
||||
return 13;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(strncmp(format, "BImm", 4) == 0);
|
||||
VIXL_ASSERT(strncmp(format, "BImm", 4) == 0);
|
||||
|
||||
int64_t offset = 0;
|
||||
switch (format[5]) {
|
||||
|
|
@ -1570,7 +1597,7 @@ int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
|||
case 'm': offset = instr->ImmCmpBranch(); break;
|
||||
// BImmTest - test and branch immediate.
|
||||
case 'e': offset = instr->ImmTestBranch(); break;
|
||||
default: UNIMPLEMENTED();
|
||||
default: VIXL_UNIMPLEMENTED();
|
||||
}
|
||||
offset <<= kInstructionSizeLog2;
|
||||
char sign = '+';
|
||||
|
|
@ -1578,15 +1605,16 @@ int Disassembler::SubstituteBranchTargetField(Instruction* instr,
|
|||
offset = -offset;
|
||||
sign = '-';
|
||||
}
|
||||
AppendToOutput("#%c0x%" PRIx64, sign, offset);
|
||||
VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
|
||||
AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, offset, instr + offset);
|
||||
return 8;
|
||||
}
|
||||
|
||||
|
||||
int Disassembler::SubstituteExtendField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(strncmp(format, "Ext", 3) == 0);
|
||||
ASSERT(instr->ExtendMode() <= 7);
|
||||
VIXL_ASSERT(strncmp(format, "Ext", 3) == 0);
|
||||
VIXL_ASSERT(instr->ExtendMode() <= 7);
|
||||
USE(format);
|
||||
|
||||
const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx",
|
||||
|
|
@ -1598,12 +1626,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
|
|||
(((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
|
||||
(instr->ExtendMode() == UXTX))) {
|
||||
if (instr->ImmExtendShift() > 0) {
|
||||
AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift());
|
||||
AppendToOutput(", lsl #%d", instr->ImmExtendShift());
|
||||
}
|
||||
} else {
|
||||
AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
|
||||
if (instr->ImmExtendShift() > 0) {
|
||||
AppendToOutput(" #%" PRId64, instr->ImmExtendShift());
|
||||
AppendToOutput(" #%d", instr->ImmExtendShift());
|
||||
}
|
||||
}
|
||||
return 3;
|
||||
|
|
@ -1612,7 +1640,7 @@ int Disassembler::SubstituteExtendField(Instruction* instr,
|
|||
|
||||
int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(strncmp(format, "Offsetreg", 9) == 0);
|
||||
VIXL_ASSERT(strncmp(format, "Offsetreg", 9) == 0);
|
||||
const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
|
||||
"undefined", "undefined", "sxtw", "sxtx" };
|
||||
USE(format);
|
||||
|
|
@ -1632,7 +1660,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
|||
if (!((ext == UXTX) && (shift == 0))) {
|
||||
AppendToOutput(", %s", extend_mode[ext]);
|
||||
if (shift != 0) {
|
||||
AppendToOutput(" #%" PRId64, instr->SizeLS());
|
||||
AppendToOutput(" #%d", instr->SizeLS());
|
||||
}
|
||||
}
|
||||
return 9;
|
||||
|
|
@ -1641,7 +1669,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
|
|||
|
||||
int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
||||
const char* format) {
|
||||
ASSERT(format[0] == 'P');
|
||||
VIXL_ASSERT(format[0] == 'P');
|
||||
USE(format);
|
||||
|
||||
int prefetch_mode = instr->PrefetchMode();
|
||||
|
|
@ -1654,6 +1682,23 @@ int Disassembler::SubstitutePrefetchField(Instruction* instr,
|
|||
return 6;
|
||||
}
|
||||
|
||||
int Disassembler::SubstituteBarrierField(Instruction* instr,
|
||||
const char* format) {
|
||||
VIXL_ASSERT(format[0] == 'M');
|
||||
USE(format);
|
||||
|
||||
static const char* options[4][4] = {
|
||||
{ "sy (0b0000)", "oshld", "oshst", "osh" },
|
||||
{ "sy (0b0100)", "nshld", "nshst", "nsh" },
|
||||
{ "sy (0b1000)", "ishld", "ishst", "ish" },
|
||||
{ "sy (0b1100)", "ld", "st", "sy" }
|
||||
};
|
||||
int domain = instr->ImmBarrierDomain();
|
||||
int type = instr->ImmBarrierType();
|
||||
|
||||
AppendToOutput("%s", options[domain][type]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
void Disassembler::ResetOutput() {
|
||||
buffer_pos_ = 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue