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omap_intc: Qdevify
Convert the omap_intc devices to qdev. This includes adding a 'revision' property which will be needed for omap3. The bulk of this patch is the replacement of "s->irq[x][y]" with "qdev_get_gpio_in(s->ih[x], y)" now that the interrupt controller exposes its input lines as qdev gpio inputs. The devices are named "omap-intc" and "omap2-intc", following the filename and the OMAP2/3 hardware names, although some internal functions are still named "omap_inth_*". Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
53bb614ee3
commit
0919ac7876
5 changed files with 221 additions and 164 deletions
129
hw/omap_intc.c
129
hw/omap_intc.c
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@ -19,7 +19,7 @@
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*/
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#include "hw.h"
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#include "omap.h"
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#include "exec-memory.h"
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#include "sysbus.h"
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/* Interrupt Handlers */
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struct omap_intr_handler_bank_s {
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@ -33,25 +33,26 @@ struct omap_intr_handler_bank_s {
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};
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struct omap_intr_handler_s {
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SysBusDevice busdev;
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qemu_irq *pins;
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qemu_irq parent_intr[2];
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MemoryRegion mmio;
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void *iclk;
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void *fclk;
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unsigned char nbanks;
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int level_only;
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uint32_t size;
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uint8_t revision;
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/* state */
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uint32_t new_agr[2];
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int sir_intr[2];
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int autoidle;
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uint32_t mask;
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struct omap_intr_handler_bank_s bank[];
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struct omap_intr_handler_bank_s bank[3];
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};
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inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n)
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{
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return s->pins[n];
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}
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static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
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{
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int i, j, sir_intr, p_intr, p, f;
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@ -325,8 +326,10 @@ static const MemoryRegionOps omap_inth_mem_ops = {
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},
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};
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void omap_inth_reset(struct omap_intr_handler_s *s)
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static void omap_inth_reset(DeviceState *dev)
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{
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struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
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sysbus_from_qdev(dev));
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int i;
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for (i = 0; i < s->nbanks; ++i){
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@ -353,29 +356,35 @@ void omap_inth_reset(struct omap_intr_handler_s *s)
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qemu_set_irq(s->parent_intr[1], 0);
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}
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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unsigned long size, unsigned char nbanks, qemu_irq **pins,
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qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
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static int omap_intc_init(SysBusDevice *dev)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
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g_malloc0(sizeof(struct omap_intr_handler_s) +
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sizeof(struct omap_intr_handler_bank_s) * nbanks);
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s->parent_intr[0] = parent_irq;
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s->parent_intr[1] = parent_fiq;
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s->nbanks = nbanks;
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s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
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if (pins)
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*pins = s->pins;
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memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s, "omap-intc", size);
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memory_region_add_subregion(get_system_memory(), base, &s->mmio);
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omap_inth_reset(s);
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return s;
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struct omap_intr_handler_s *s;
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s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
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if (!s->iclk) {
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hw_error("omap-intc: clk not connected\n");
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}
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s->nbanks = 1;
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sysbus_init_irq(dev, &s->parent_intr[0]);
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sysbus_init_irq(dev, &s->parent_intr[1]);
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qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
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memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
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"omap-intc", s->size);
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sysbus_init_mmio_region(dev, &s->mmio);
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return 0;
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}
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static SysBusDeviceInfo omap_intc_info = {
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.init = omap_intc_init,
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.qdev.name = "omap-intc",
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.qdev.size = sizeof(struct omap_intr_handler_s),
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.qdev.reset = omap_inth_reset,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
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DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
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DEFINE_PROP_END_OF_LIST()
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}
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};
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static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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@ -394,7 +403,7 @@ static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
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switch (offset) {
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case 0x00: /* INTC_REVISION */
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return 0x21;
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return s->revision;
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case 0x10: /* INTC_SYSCONFIG */
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return (s->autoidle >> 2) & 1;
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@ -475,7 +484,7 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
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s->autoidle &= 4;
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s->autoidle |= (value & 1) << 2;
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if (value & 2) /* SOFTRESET */
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omap_inth_reset(s);
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omap_inth_reset(&s->busdev.qdev);
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return;
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case 0x48: /* INTC_CONTROL */
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@ -568,27 +577,45 @@ static const MemoryRegionOps omap2_inth_mem_ops = {
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},
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};
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struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
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int size, int nbanks, qemu_irq **pins,
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qemu_irq parent_irq, qemu_irq parent_fiq,
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omap_clk fclk, omap_clk iclk)
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static int omap2_intc_init(SysBusDevice *dev)
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
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g_malloc0(sizeof(struct omap_intr_handler_s) +
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sizeof(struct omap_intr_handler_bank_s) * nbanks);
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s->parent_intr[0] = parent_irq;
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s->parent_intr[1] = parent_fiq;
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s->nbanks = nbanks;
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struct omap_intr_handler_s *s;
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s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
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if (!s->iclk) {
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hw_error("omap2-intc: iclk not connected\n");
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}
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if (!s->fclk) {
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hw_error("omap2-intc: fclk not connected\n");
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}
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s->level_only = 1;
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s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
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if (pins)
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*pins = s->pins;
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memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);
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memory_region_add_subregion(get_system_memory(), base, &s->mmio);
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omap_inth_reset(s);
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return s;
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s->nbanks = 3;
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sysbus_init_irq(dev, &s->parent_intr[0]);
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sysbus_init_irq(dev, &s->parent_intr[1]);
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qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
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memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
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"omap2-intc", 0x1000);
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sysbus_init_mmio_region(dev, &s->mmio);
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return 0;
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}
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static SysBusDeviceInfo omap2_intc_info = {
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.init = omap2_intc_init,
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.qdev.name = "omap2-intc",
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.qdev.size = sizeof(struct omap_intr_handler_s),
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.qdev.reset = omap_inth_reset,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
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revision, 0x21),
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DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
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DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
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DEFINE_PROP_END_OF_LIST()
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}
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};
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static void omap_intc_register_device(void)
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{
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sysbus_register_withprop(&omap_intc_info);
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sysbus_register_withprop(&omap2_intc_info);
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}
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device_init(omap_intc_register_device)
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