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target/riscv: rvv-1.0: index load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
Alistair Francis
parent
79556fb6fa
commit
08b9d0ed4a
4 changed files with 142 additions and 148 deletions
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@ -217,15 +217,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
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cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
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}
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GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
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GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
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GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
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GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
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GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
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GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
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GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
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GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
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GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
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GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
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GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
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GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
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@ -393,8 +384,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
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void *vs2, CPURISCVState *env, uint32_t desc,
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vext_get_index_addr get_index_addr,
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vext_ldst_elem_fn *ldst_elem,
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uint32_t esz, uint32_t msz, uintptr_t ra,
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MMUAccessType access_type)
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uint32_t esz, uintptr_t ra, MMUAccessType access_type)
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{
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uint32_t i, k;
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uint32_t nf = vext_nf(desc);
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@ -406,7 +396,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
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if (!vm && !vext_elem_mask(v0, i)) {
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continue;
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}
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probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
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probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
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access_type);
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}
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/* load bytes from guest memory */
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@ -416,67 +406,63 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
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continue;
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}
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while (k < nf) {
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abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
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abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
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ldst_elem(env, addr, i + k * vlmax, vd, ra);
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k++;
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}
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}
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}
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#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \
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#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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void *vs2, CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
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LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \
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GETPC(), MMU_DATA_LOAD); \
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LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
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}
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GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b)
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GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h)
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GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w)
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GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d)
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GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h)
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GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w)
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GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d)
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GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w)
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GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d)
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GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b)
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GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h)
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GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w)
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GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d)
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GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b)
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GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h)
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GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w)
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GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d)
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GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h)
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GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w)
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GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d)
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GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w)
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GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d)
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GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
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GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h)
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GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w)
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GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d)
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GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b)
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GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h)
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GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w)
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GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d)
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GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b)
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GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h)
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GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w)
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GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d)
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GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b)
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GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h)
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GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w)
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GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d)
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#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
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#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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void *vs2, CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
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STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \
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STORE_FN, sizeof(ETYPE), \
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GETPC(), MMU_DATA_STORE); \
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}
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GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
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GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
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GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
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GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
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GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
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GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
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GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
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GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
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GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
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GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
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GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
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GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
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GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
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GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
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GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
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GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
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GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
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GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
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GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
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GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
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GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
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GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
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GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
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GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
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GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
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GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
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GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
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GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
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GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
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/*
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*** unit-stride fault-only-fisrt load instructions
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