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hw/intc/arm_gicv3: Add state information
Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-7-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled: * Add missing qom/cpu.h include * Remove legacy-only state fields (we can add them later if/when we add legacy emulation) * Use arrays of uint32_t to store the various distributor bitmaps, and provide accessor functions for the various set/test/etc operations * Add various missing register offset #defines * Accessor macros which combine distributor and redistributor behaviour removed * Fields in state structures renamed to match architectural register names * Corrected the reset value for GICR_IENABLER0 since we don't support legacy mode * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in non-secure" so that we can fake up the firmware-mandated reconfiguration only when we need it ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
This commit is contained in:
Pavel Fedin
Peter Maydell
parent
15a21fe028
commit
07e2034d08
3 changed files with 518 additions and 5 deletions
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@ -3,8 +3,9 @@
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*
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* Copyright (c) 2012 Linaro Limited
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Peter Maydell
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* Extended to 64 cores by Shlomo Pongratz
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* Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -26,7 +27,143 @@
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#include "hw/sysbus.h"
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#include "hw/intc/arm_gic_common.h"
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typedef struct GICv3State {
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/*
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* Maximum number of possible interrupts, determined by the GIC architecture.
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* Note that this does not include LPIs. When implemented, these should be
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* dealt with separately.
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*/
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#define GICV3_MAXIRQ 1020
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#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
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/* Minimum BPR for Secure, or when security not enabled */
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#define GIC_MIN_BPR 0
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/* Minimum BPR for Nonsecure when security is enabled */
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#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
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/* For some distributor fields we want to model the array of 32-bit
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* register values which hold various bitmaps corresponding to enabled,
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* pending, etc bits. These macros and functions facilitate that; the
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* APIs are generally modelled on the generic bitmap.h functions
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* (which are unsuitable here because they use 'unsigned long' as the
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* underlying storage type, which is very awkward when you need to
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* access the data as 32-bit values.)
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* Each bitmap contains a bit for each interrupt. Although there is
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* space for the PPIs and SGIs, those bits (the first 32) are never
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* used as that state lives in the redistributor. The unused bits are
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* provided purely so that interrupt X's state is always in bit X; this
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* avoids bugs where we forget to subtract GIC_INTERNAL from an
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* interrupt number.
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*/
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#define GICV3_BMP_SIZE (DIV_ROUND_UP(GICV3_MAXIRQ, 32))
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#define GIC_DECLARE_BITMAP(name) \
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uint32_t name[GICV3_BMP_SIZE]
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#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
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#define GIC_BIT_WORD(nr) ((nr) / 32)
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static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
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{
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uint32_t mask = GIC_BIT_MASK(nr);
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uint32_t *p = addr + GIC_BIT_WORD(nr);
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*p |= mask;
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}
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static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
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{
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uint32_t mask = GIC_BIT_MASK(nr);
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uint32_t *p = addr + GIC_BIT_WORD(nr);
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*p &= ~mask;
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}
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static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
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{
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return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
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}
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static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
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{
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uint32_t mask = GIC_BIT_MASK(nr);
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uint32_t *p = addr + GIC_BIT_WORD(nr);
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*p &= ~mask;
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*p |= (val & 1U) << (nr % 32);
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}
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/* Return a pointer to the 32-bit word containing the specified bit. */
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static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
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{
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return addr + GIC_BIT_WORD(nr);
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}
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typedef struct GICv3State GICv3State;
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typedef struct GICv3CPUState GICv3CPUState;
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/* Some CPU interface registers come in three flavours:
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* Group0, Group1 (Secure) and Group1 (NonSecure)
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* (where the latter two are exposed as a single banked system register).
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* In the state struct they are implemented as a 3-element array which
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* can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
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* If the CPU doesn't support EL3 then the G1 element is unused.
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*
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* These constants are also used to communicate the group to use for
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* an interrupt or SGI when it is passed between the cpu interface and
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* the redistributor or distributor. For those purposes the receiving end
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* must be prepared to cope with a Group 1 Secure interrupt even if it does
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* not have security support enabled, because security can be disabled
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* independently in the CPU and in the GIC. In that case the receiver should
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* treat an incoming Group 1 Secure interrupt as if it were Group 0.
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* (This architectural requirement is why the _G1 element is the unused one
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* in a no-EL3 CPU: we would otherwise have to translate back and forth
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* between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
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*/
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#define GICV3_G0 0
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#define GICV3_G1 1
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#define GICV3_G1NS 2
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/* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
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* group-related, so those indices are just 0 for S and 1 for NS.
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* (If the CPU or the GIC, respectively, don't support the Security
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* extensions then the S element is unused.)
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*/
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#define GICV3_S 0
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#define GICV3_NS 1
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struct GICv3CPUState {
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GICv3State *gic;
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CPUState *cpu;
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/* Redistributor */
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uint32_t level; /* Current IRQ level */
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/* RD_base page registers */
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uint32_t gicr_ctlr;
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uint64_t gicr_typer;
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uint32_t gicr_statusr[2];
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uint32_t gicr_waker;
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uint64_t gicr_propbaser;
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uint64_t gicr_pendbaser;
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/* SGI_base page registers */
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uint32_t gicr_igroupr0;
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uint32_t gicr_ienabler0;
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uint32_t gicr_ipendr0;
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uint32_t gicr_iactiver0;
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uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
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uint32_t gicr_igrpmodr0;
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uint32_t gicr_nsacr;
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uint8_t gicr_ipriorityr[GIC_INTERNAL];
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/* CPU interface */
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uint64_t icc_ctlr_el1[2];
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uint64_t icc_pmr_el1;
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uint64_t icc_bpr[3];
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uint64_t icc_apr[3][4];
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uint64_t icc_igrpen[3];
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uint64_t icc_ctlr_el3;
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};
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struct GICv3State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -41,9 +178,58 @@ typedef struct GICv3State {
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uint32_t num_irq;
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uint32_t revision;
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bool security_extn;
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bool irq_reset_nonsecure;
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int dev_fd; /* kvm device fd if backed by kvm vgic support */
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} GICv3State;
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Error *migration_blocker;
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/* Distributor */
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/* for a GIC with the security extensions the NS banked version of this
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* register is just an alias of bit 1 of the S banked version.
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*/
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uint32_t gicd_ctlr;
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uint32_t gicd_statusr[2];
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GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */
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GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */
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GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */
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GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */
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GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */
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GIC_DECLARE_BITMAP(level); /* Current level */
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GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
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uint8_t gicd_ipriority[GICV3_MAXIRQ];
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uint64_t gicd_irouter[GICV3_MAXIRQ];
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uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
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GICv3CPUState *cpu;
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};
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#define GICV3_BITMAP_ACCESSORS(BMP) \
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static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
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{ \
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gic_bmp_set_bit(irq, s->BMP); \
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} \
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static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
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{ \
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return gic_bmp_test_bit(irq, s->BMP); \
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} \
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static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
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{ \
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gic_bmp_clear_bit(irq, s->BMP); \
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} \
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static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
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int irq, int value) \
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{ \
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gic_bmp_replace_bit(irq, s->BMP, value); \
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}
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GICV3_BITMAP_ACCESSORS(group)
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GICV3_BITMAP_ACCESSORS(grpmod)
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GICV3_BITMAP_ACCESSORS(enabled)
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GICV3_BITMAP_ACCESSORS(pending)
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GICV3_BITMAP_ACCESSORS(active)
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GICV3_BITMAP_ACCESSORS(level)
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GICV3_BITMAP_ACCESSORS(edge_trigger)
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#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
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#define ARM_GICV3_COMMON(obj) \
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