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target/riscv: Convert quadrant 1 of RVXC insns to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
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07b001c6fc
3 changed files with 195 additions and 117 deletions
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@ -73,3 +73,154 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
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return false;
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#endif
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}
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static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
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{
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if (a->imm == 0) {
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/* Hint: insn is valid but does not affect state */
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return true;
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}
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arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
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return trans_addi(ctx, &arg);
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}
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static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
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{
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#ifdef TARGET_RISCV32
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/* C.JAL */
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arg_jal arg = { .rd = 1, .imm = a->imm };
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return trans_jal(ctx, &arg);
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#else
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/* C.ADDIW */
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arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
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return trans_addiw(ctx, &arg);
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#endif
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}
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static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
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{
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if (a->rd == 0) {
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/* Hint: insn is valid but does not affect state */
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return true;
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}
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arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
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return trans_addi(ctx, &arg);
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}
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static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
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{
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if (a->rd == 2) {
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/* C.ADDI16SP */
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arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
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return trans_addi(ctx, &arg);
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} else if (a->imm_lui != 0) {
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/* C.LUI */
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if (a->rd == 0) {
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/* Hint: insn is valid but does not affect state */
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return true;
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}
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arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
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return trans_lui(ctx, &arg);
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}
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return false;
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}
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static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
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{
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int shamt = a->shamt;
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if (shamt == 0) {
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/* For RV128 a shamt of 0 means a shift by 64 */
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shamt = 64;
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}
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/* Ensure, that shamt[5] is zero for RV32 */
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if (shamt >= TARGET_LONG_BITS) {
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return false;
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}
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arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
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return trans_srli(ctx, &arg);
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}
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static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
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{
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int shamt = a->shamt;
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if (shamt == 0) {
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/* For RV128 a shamt of 0 means a shift by 64 */
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shamt = 64;
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}
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/* Ensure, that shamt[5] is zero for RV32 */
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if (shamt >= TARGET_LONG_BITS) {
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return false;
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}
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arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
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return trans_srai(ctx, &arg);
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}
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static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
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{
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arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
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return trans_andi(ctx, &arg);
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}
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static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
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{
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arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_sub(ctx, &arg);
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}
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static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
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{
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arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_xor(ctx, &arg);
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}
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static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
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{
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arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_or(ctx, &arg);
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}
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static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
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{
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arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_and(ctx, &arg);
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}
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static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
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{
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#ifdef TARGET_RISCV64
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arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_subw(ctx, &arg);
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#else
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return false;
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#endif
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}
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static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
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{
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#ifdef TARGET_RISCV64
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arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_addw(ctx, &arg);
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#else
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return false;
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#endif
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}
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static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
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{
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arg_jal arg = { .rd = 0, .imm = a->imm };
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return trans_jal(ctx, &arg);
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}
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static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
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{
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arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
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return trans_beq(ctx, &arg);
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}
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static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
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{
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arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
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return trans_bne(ctx, &arg);
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}
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