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target/arm: Implement SVE floating-point exponential accelerator

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:09 +01:00 • committed by Peter Maydell
parent 4b242d9c1b
commit 0762cd428f
4 changed files with 125 additions and 0 deletions
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7
target/arm/sve.decode
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@ -66,6 +66,7 @@
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
# Three operand with unused vector element size
@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
@ -288,6 +289,12 @@ ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
### SVE Integer Misc - Unpredicated Group
# SVE floating-point exponential accelerator
# Note esz != 0
FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
### SVE Predicate Logical Operations Group
# SVE predicate logical operations