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target-arm queue:

Browse source 
* Fix physical address resolution for Stage2
  * pl011: refactoring, implement reset method
  * Support GICv3 with hvf acceleration
  * sbsa-ref: remove cortex-a76 from list of supported cpus
  * Correct syndrome for ATS12NSO* traps at Secure EL1
  * Fix priority of HSTR_EL2 traps vs UNDEFs
  * Implement FEAT_FGT for '-cpu max'
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Merge tag 'pull-target-arm-20230203' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix physical address resolution for Stage2
 * pl011: refactoring, implement reset method
 * Support GICv3 with hvf acceleration
 * sbsa-ref: remove cortex-a76 from list of supported cpus
 * Correct syndrome for ATS12NSO* traps at Secure EL1
 * Fix priority of HSTR_EL2 traps vs UNDEFs
 * Implement FEAT_FGT for '-cpu max'

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# gpg: Signature made Fri 03 Feb 2023 14:28:59 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230203' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
  target/arm: Enable FEAT_FGT on '-cpu max'
  target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
  target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
  target/arm: Implement the HFGITR_EL2.ERET trap
  target/arm: Mark up sysregs for HFGITR bits 48..63
  target/arm: Mark up sysregs for HFGITR bits 18..47
  target/arm: Mark up sysregs for HFGITR bits 12..17
  target/arm: Mark up sysregs for HFGITR bits 0..11
  target/arm: Mark up sysregs for HDFGRTR bits 12..63
  target/arm: Mark up sysregs for HDFGRTR bits 0..11
  target/arm: Mark up sysregs for HFGRTR bits 36..63
  target/arm: Mark up sysregs for HFGRTR bits 24..35
  target/arm: Mark up sysregs for HFGRTR bits 12..23
  target/arm: Mark up sysregs for HFGRTR bits 0..11
  target/arm: Implement FGT trapping infrastructure
  target/arm: Define the FEAT_FGT registers
  target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
  target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
  target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
  target/arm: Move do_coproc_insn() syndrome calculation earlier
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-02-03 15:33:05 +00:00
commit 0730eab4d3
21 changed files with 1340 additions and 189 deletions
Download patch file Download diff file Expand all files Collapse all files

15
include/hw/arm/virt.h
View file

@ -109,14 +109,19 @@ typedef enum VirtMSIControllerType {
} VirtMSIControllerType;
typedef enum VirtGICType {
VIRT_GIC_VERSION_MAX,
VIRT_GIC_VERSION_HOST,
VIRT_GIC_VERSION_2,
VIRT_GIC_VERSION_3,
VIRT_GIC_VERSION_4,
VIRT_GIC_VERSION_MAX = 0,
VIRT_GIC_VERSION_HOST = 1,
/* The concrete GIC values have to match the GIC version number */
VIRT_GIC_VERSION_2 = 2,
VIRT_GIC_VERSION_3 = 3,
VIRT_GIC_VERSION_4 = 4,
VIRT_GIC_VERSION_NOSEL,
} VirtGICType;
#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
struct VirtMachineClass {
MachineClass parent;
bool disallow_affinity_adjustment;

5
include/hw/char/pl011.h
View file

@ -27,6 +27,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
/* This shares the same struct (and cast macro) as the base pl011 device */
#define TYPE_PL011_LUMINARY "pl011_luminary"
/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
#define PL011_FIFO_DEPTH 16
struct PL011State {
SysBusDevice parent_obj;
@ -39,7 +42,7 @@ struct PL011State {
uint32_t dmacr;
uint32_t int_enabled;
uint32_t int_level;
uint32_t read_fifo[16];
uint32_t read_fifo[PL011_FIFO_DEPTH];
uint32_t ilpr;
uint32_t ibrd;
uint32_t fbrd;