hw: arm: allwinner-sramc: Add SRAM Controller support for R40

Only a few important registers are added, especially the SRAM_VER
register.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao 2023-06-06 10:19:33 +01:00 committed by Peter Maydell
parent 0de1b69315
commit 05def917e1
8 changed files with 271 additions and 1 deletions

View file

@ -27,6 +27,7 @@
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
#include "hw/misc/allwinner-r40-dramc.h"
#include "hw/misc/allwinner-sramc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "hw/net/allwinner_emac.h"
#include "hw/net/allwinner-sun8i-emac.h"
@ -38,6 +39,7 @@ enum {
AW_R40_DEV_SRAM_A2,
AW_R40_DEV_SRAM_A3,
AW_R40_DEV_SRAM_A4,
AW_R40_DEV_SRAMC,
AW_R40_DEV_EMAC,
AW_R40_DEV_MMC0,
AW_R40_DEV_MMC1,
@ -102,6 +104,7 @@ struct AwR40State {
ARMCPU cpus[AW_R40_NUM_CPUS];
const hwaddr *memmap;
AwSRAMCState sramc;
AwA10PITState timer;
AwSdHostState mmc[AW_R40_NUM_MMCS];
AwR40ClockCtlState ccu;

View file

@ -0,0 +1,69 @@
/*
* Allwinner SRAM controller emulation
*
* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_MISC_ALLWINNER_SRAMC_H
#define HW_MISC_ALLWINNER_SRAMC_H
#include "qom/object.h"
#include "hw/sysbus.h"
#include "qemu/uuid.h"
/**
* Object model
* @{
*/
#define TYPE_AW_SRAMC "allwinner-sramc"
#define TYPE_AW_SRAMC_SUN8I_R40 TYPE_AW_SRAMC "-sun8i-r40"
OBJECT_DECLARE_TYPE(AwSRAMCState, AwSRAMCClass, AW_SRAMC)
/** @} */
/**
* Allwinner SRAMC object instance state
*/
struct AwSRAMCState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
/** Maps I/O registers in physical memory */
MemoryRegion iomem;
/* registers */
uint32_t sram_ctl1;
uint32_t sram_ver;
uint32_t sram_soft_entry_reg0;
};
/**
* Allwinner SRAM Controller class-level struct.
*
* This struct is filled by each sunxi device specific code
* such that the generic code can use this struct to support
* all devices.
*/
struct AwSRAMCClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
uint32_t sram_version_code;
};
#endif /* HW_MISC_ALLWINNER_SRAMC_H */