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target-tilegx: Handle atomic instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
03b217b168
commit
0583b23323
3 changed files with 248 additions and 2 deletions
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@ -61,6 +61,7 @@ typedef struct {
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int num_wb;
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int mmuidx;
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bool exit_tb;
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TileExcp atomic_excp;
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struct {
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TCGCond cond; /* branch condition */
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@ -180,6 +181,32 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
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tcg_temp_free(t0);
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}
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static void gen_atomic_excp(DisasContext *dc, unsigned dest, TCGv tdest,
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TCGv tsrca, TCGv tsrcb, TileExcp excp)
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{
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#ifdef CONFIG_USER_ONLY
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TCGv_i32 t;
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tcg_gen_st_tl(tsrca, cpu_env, offsetof(CPUTLGState, atomic_srca));
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tcg_gen_st_tl(tsrcb, cpu_env, offsetof(CPUTLGState, atomic_srcb));
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t = tcg_const_i32(dest);
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, atomic_dstr));
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tcg_temp_free_i32(t);
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/* We're going to write the real result in the exception. But in
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the meantime we've already created a writeback register, and
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we don't want that to remain uninitialized. */
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tcg_gen_movi_tl(tdest, 0);
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/* Note that we need to delay issuing the exception that implements
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the atomic operation until after writing back the results of the
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instruction occupying the X0 pipe. */
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dc->atomic_excp = excp;
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#else
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gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
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#endif
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}
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/* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
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specified by the bottom 3 bits of TSRCB, and set TDEST to the
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low 64 bits of the resulting value. */
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@ -591,8 +618,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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mnemonic = "cmpeq";
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break;
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case OE_RRR(CMPEXCH4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_CMPEXCH4);
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mnemonic = "cmpexch4";
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break;
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case OE_RRR(CMPEXCH, 0, X1):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_CMPEXCH);
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mnemonic = "cmpexch";
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break;
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case OE_RRR(CMPLES, 0, X0):
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case OE_RRR(CMPLES, 0, X1):
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case OE_RRR(CMPLES, 2, Y0):
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@ -658,7 +692,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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mnemonic = "dblalign";
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break;
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case OE_RRR(EXCH4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_EXCH4);
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mnemonic = "exch4";
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break;
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case OE_RRR(EXCH, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_EXCH);
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mnemonic = "exch";
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break;
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case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
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case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
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case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
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@ -667,14 +709,47 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
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case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
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case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
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case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
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return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
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case OE_RRR(FETCHADD4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHADD4);
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mnemonic = "fetchadd4";
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break;
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case OE_RRR(FETCHADDGEZ4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ4);
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mnemonic = "fetchaddgez4";
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break;
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case OE_RRR(FETCHADDGEZ, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ);
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mnemonic = "fetchaddgez";
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break;
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case OE_RRR(FETCHADD, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHADD);
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mnemonic = "fetchadd";
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break;
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case OE_RRR(FETCHAND4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHAND4);
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mnemonic = "fetchand4";
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break;
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case OE_RRR(FETCHAND, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHAND);
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mnemonic = "fetchand";
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break;
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case OE_RRR(FETCHOR4, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHOR4);
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mnemonic = "fetchor4";
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break;
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case OE_RRR(FETCHOR, 0, X1):
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gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
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TILEGX_EXCP_OPCODE_FETCHOR);
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mnemonic = "fetchor";
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break;
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case OE_RRR(FSINGLE_ADD1, 0, X0):
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case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
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case OE_RRR(FSINGLE_MUL1, 0, X0):
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@ -1936,6 +2011,8 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
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tcg_temp_free_i64(dc->jmp.dest);
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tcg_gen_exit_tb(0);
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dc->exit_tb = true;
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} else if (dc->atomic_excp != TILEGX_EXCP_NONE) {
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gen_exception(dc, dc->atomic_excp);
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}
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}
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@ -1956,6 +2033,7 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
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dc->pc = pc_start;
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dc->mmuidx = 0;
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dc->exit_tb = false;
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dc->atomic_excp = TILEGX_EXCP_NONE;
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dc->jmp.cond = TCG_COND_NEVER;
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TCGV_UNUSED_I64(dc->jmp.dest);
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TCGV_UNUSED_I64(dc->jmp.val1);
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