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target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-same and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE, FACGT, FMLA and FMLS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
67d43538ae
commit
057d5f62f8
5 changed files with 130 additions and 4 deletions
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@ -6045,18 +6045,33 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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switch (fpopcode) {
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case 0x39: /* FMLS */
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/* As usual for ARM, separate negation for fused multiply-add */
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gen_helper_vfp_negd(tcg_op1, tcg_op1);
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/* fall through */
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case 0x19: /* FMLA */
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read_vec_element(s, tcg_res, rd, pass, MO_64);
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gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
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tcg_res, fpst);
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break;
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case 0x18: /* FMAXNM */
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gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1a: /* FADD */
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gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1b: /* FMULX */
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gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1c: /* FCMEQ */
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gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1e: /* FMAX */
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gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1f: /* FRECPS */
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gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x38: /* FMINNM */
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gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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@ -6066,12 +6081,18 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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case 0x3e: /* FMIN */
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gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3f: /* FRSQRTS */
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gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5b: /* FMUL */
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gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5c: /* FCMGE */
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gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5d: /* FACGE */
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gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5f: /* FDIV */
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gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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@ -6082,6 +6103,9 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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case 0x7c: /* FCMGT */
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gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7d: /* FACGT */
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gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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default:
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g_assert_not_reached();
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}
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@ -6101,15 +6125,30 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
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switch (fpopcode) {
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case 0x39: /* FMLS */
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/* As usual for ARM, separate negation for fused multiply-add */
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gen_helper_vfp_negs(tcg_op1, tcg_op1);
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/* fall through */
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case 0x19: /* FMLA */
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read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
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tcg_res, fpst);
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break;
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case 0x1a: /* FADD */
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gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1b: /* FMULX */
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gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1c: /* FCMEQ */
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gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1e: /* FMAX */
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gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1f: /* FRECPS */
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gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x18: /* FMAXNM */
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gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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@ -6122,12 +6161,18 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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case 0x3e: /* FMIN */
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gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3f: /* FRSQRTS */
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gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5b: /* FMUL */
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gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5c: /* FCMGE */
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gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5d: /* FACGE */
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gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5f: /* FDIV */
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gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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@ -6138,6 +6183,9 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
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case 0x7c: /* FCMGT */
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gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7d: /* FACGT */
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gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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default:
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g_assert_not_reached();
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}
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@ -6192,8 +6240,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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case 0x3f: /* FRSQRTS */
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case 0x5d: /* FACGE */
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case 0x7d: /* FACGT */
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unsupported_encoding(s, insn);
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return;
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case 0x1c: /* FCMEQ */
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case 0x5c: /* FCMGE */
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case 0x7c: /* FCMGT */
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@ -7303,8 +7349,6 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
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case 0x7d: /* FACGT */
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case 0x19: /* FMLA */
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case 0x39: /* FMLS */
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unsupported_encoding(s, insn);
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return;
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case 0x18: /* FMAXNM */
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case 0x1a: /* FADD */
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case 0x1c: /* FCMEQ */
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