mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 00:03:54 -06:00
SVM Support, by Alexander Graf.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3210 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
bbbb2f0af9
commit
0573fbfc3f
9 changed files with 921 additions and 15 deletions
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@ -594,7 +594,18 @@ static void do_interrupt_protected(int intno, int is_int, int error_code,
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int has_error_code, new_stack, shift;
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uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
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uint32_t old_eip, sp_mask;
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int svm_should_check = 1;
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if ((env->intercept & INTERCEPT_SVM_MASK) && !is_int && next_eip==-1) {
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next_eip = EIP;
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svm_should_check = 0;
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}
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if (svm_should_check
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&& (INTERCEPTEDl(_exceptions, 1 << intno)
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&& !is_int)) {
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raise_interrupt(intno, is_int, error_code, 0);
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}
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has_error_code = 0;
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if (!is_int && !is_hw) {
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switch(intno) {
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@ -830,7 +841,17 @@ static void do_interrupt64(int intno, int is_int, int error_code,
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int has_error_code, new_stack;
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uint32_t e1, e2, e3, ss;
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target_ulong old_eip, esp, offset;
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int svm_should_check = 1;
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if ((env->intercept & INTERCEPT_SVM_MASK) && !is_int && next_eip==-1) {
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next_eip = EIP;
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svm_should_check = 0;
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}
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if (svm_should_check
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&& INTERCEPTEDl(_exceptions, 1 << intno)
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&& !is_int) {
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raise_interrupt(intno, is_int, error_code, 0);
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}
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has_error_code = 0;
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if (!is_int && !is_hw) {
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switch(intno) {
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@ -1077,7 +1098,17 @@ static void do_interrupt_real(int intno, int is_int, int error_code,
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int selector;
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uint32_t offset, esp;
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uint32_t old_cs, old_eip;
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int svm_should_check = 1;
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if ((env->intercept & INTERCEPT_SVM_MASK) && !is_int && next_eip==-1) {
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next_eip = EIP;
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svm_should_check = 0;
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}
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if (svm_should_check
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&& INTERCEPTEDl(_exceptions, 1 << intno)
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&& !is_int) {
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raise_interrupt(intno, is_int, error_code, 0);
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}
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/* real mode (simpler !) */
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dt = &env->idt;
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if (intno * 4 + 3 > dt->limit)
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@ -1227,8 +1258,10 @@ int check_exception(int intno, int *error_code)
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void raise_interrupt(int intno, int is_int, int error_code,
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int next_eip_addend)
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{
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if (!is_int)
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if (!is_int) {
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svm_check_intercept_param(SVM_EXIT_EXCP_BASE + intno, error_code);
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intno = check_exception(intno, &error_code);
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}
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env->exception_index = intno;
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env->error_code = error_code;
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@ -1671,7 +1704,7 @@ void helper_cpuid(void)
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case 0x80000001:
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EAX = env->cpuid_features;
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EBX = 0;
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ECX = 0;
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ECX = env->cpuid_ext3_features;
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EDX = env->cpuid_ext2_features;
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break;
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case 0x80000002:
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@ -2745,6 +2778,9 @@ void helper_wrmsr(void)
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case MSR_PAT:
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env->pat = val;
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break;
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case MSR_VM_HSAVE_PA:
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env->vm_hsave = val;
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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env->lstar = val;
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@ -2796,6 +2832,9 @@ void helper_rdmsr(void)
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case MSR_PAT:
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val = env->pat;
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break;
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case MSR_VM_HSAVE_PA:
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val = env->vm_hsave;
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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val = env->lstar;
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@ -3877,3 +3916,483 @@ void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
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}
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env = saved_env;
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}
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/* Secure Virtual Machine helpers */
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void helper_stgi(void)
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{
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env->hflags |= HF_GIF_MASK;
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}
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void helper_clgi(void)
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{
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env->hflags &= ~HF_GIF_MASK;
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}
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#if defined(CONFIG_USER_ONLY)
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void helper_vmrun(target_ulong addr) { }
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void helper_vmmcall(void) { }
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void helper_vmload(target_ulong addr) { }
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void helper_vmsave(target_ulong addr) { }
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void helper_skinit(void) { }
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void helper_invlpga(void) { }
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void vmexit(uint64_t exit_code, uint64_t exit_info_1) { }
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int svm_check_intercept_param(uint32_t type, uint64_t param)
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{
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return 0;
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}
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#else
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static inline uint32_t
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vmcb2cpu_attrib(uint16_t vmcb_attrib, uint32_t vmcb_base, uint32_t vmcb_limit)
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{
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return ((vmcb_attrib & 0x00ff) << 8) /* Type, S, DPL, P */
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| ((vmcb_attrib & 0x0f00) << 12) /* AVL, L, DB, G */
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| ((vmcb_base >> 16) & 0xff) /* Base 23-16 */
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| (vmcb_base & 0xff000000) /* Base 31-24 */
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| (vmcb_limit & 0xf0000); /* Limit 19-16 */
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}
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static inline uint16_t cpu2vmcb_attrib(uint32_t cpu_attrib)
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{
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return ((cpu_attrib >> 8) & 0xff) /* Type, S, DPL, P */
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| ((cpu_attrib & 0xf00000) >> 12); /* AVL, L, DB, G */
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}
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extern uint8_t *phys_ram_base;
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void helper_vmrun(target_ulong addr)
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{
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uint32_t event_inj;
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uint32_t int_ctl;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile,"vmrun! " TARGET_FMT_lx "\n", addr);
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env->vm_vmcb = addr;
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regs_to_env();
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/* save the current CPU state in the hsave page */
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base), env->gdt.base);
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stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit), env->gdt.limit);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base), env->idt.base);
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stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit), env->idt.limit);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr8), env->cr[8]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags), compute_eflags());
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SVM_SAVE_SEG(env->vm_hsave, segs[R_ES], es);
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SVM_SAVE_SEG(env->vm_hsave, segs[R_CS], cs);
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SVM_SAVE_SEG(env->vm_hsave, segs[R_SS], ss);
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SVM_SAVE_SEG(env->vm_hsave, segs[R_DS], ds);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip), EIP);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), EAX);
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/* load the interception bitmaps so we do not need to access the
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vmcb in svm mode */
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/* We shift all the intercept bits so we can OR them with the TB
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flags later on */
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env->intercept = (ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept)) << INTERCEPT_INTR) | INTERCEPT_SVM_MASK;
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env->intercept_cr_read = lduw_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_cr_read));
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env->intercept_cr_write = lduw_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_cr_write));
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env->intercept_dr_read = lduw_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_dr_read));
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env->intercept_dr_write = lduw_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_dr_write));
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env->intercept_exceptions = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_exceptions));
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env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base));
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env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit));
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env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base));
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env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit));
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/* clear exit_info_2 so we behave like the real hardware */
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stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
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cpu_x86_update_cr0(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr0)));
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cpu_x86_update_cr4(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4)));
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cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3)));
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env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
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int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
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if (int_ctl & V_INTR_MASKING_MASK) {
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env->cr[8] = int_ctl & V_TPR_MASK;
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if (env->eflags & IF_MASK)
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env->hflags |= HF_HIF_MASK;
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}
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#ifdef TARGET_X86_64
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env->efer = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer));
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env->hflags &= ~HF_LMA_MASK;
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if (env->efer & MSR_EFER_LMA)
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env->hflags |= HF_LMA_MASK;
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#endif
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env->eflags = 0;
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load_eflags(ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags)),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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CC_OP = CC_OP_EFLAGS;
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CC_DST = 0xffffffff;
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SVM_LOAD_SEG(env->vm_vmcb, ES, es);
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SVM_LOAD_SEG(env->vm_vmcb, CS, cs);
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SVM_LOAD_SEG(env->vm_vmcb, SS, ss);
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SVM_LOAD_SEG(env->vm_vmcb, DS, ds);
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EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
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env->eip = EIP;
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ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
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EAX = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
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env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
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env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
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cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl)));
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/* FIXME: guest state consistency checks */
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switch(ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
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case TLB_CONTROL_DO_NOTHING:
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break;
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case TLB_CONTROL_FLUSH_ALL_ASID:
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/* FIXME: this is not 100% correct but should work for now */
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tlb_flush(env, 1);
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break;
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}
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helper_stgi();
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regs_to_env();
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/* maybe we need to inject an event */
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event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj));
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if (event_inj & SVM_EVTINJ_VALID) {
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uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK;
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uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR;
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uint32_t event_inj_err = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err));
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stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), event_inj & ~SVM_EVTINJ_VALID);
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "Injecting(%#hx): ", valid_err);
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/* FIXME: need to implement valid_err */
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switch (event_inj & SVM_EVTINJ_TYPE_MASK) {
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case SVM_EVTINJ_TYPE_INTR:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 1;
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env->exception_next_eip = -1;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "INTR");
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break;
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case SVM_EVTINJ_TYPE_NMI:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 1;
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env->exception_next_eip = EIP;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "NMI");
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break;
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case SVM_EVTINJ_TYPE_EXEPT:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 0;
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env->exception_next_eip = -1;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "EXEPT");
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break;
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case SVM_EVTINJ_TYPE_SOFT:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 1;
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env->exception_next_eip = EIP;
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "SOFT");
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break;
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}
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, " %#x %#x\n", env->exception_index, env->error_code);
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}
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if (int_ctl & V_IRQ_MASK)
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env->interrupt_request |= CPU_INTERRUPT_VIRQ;
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cpu_loop_exit();
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}
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void helper_vmmcall(void)
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{
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile,"vmmcall!\n");
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}
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void helper_vmload(target_ulong addr)
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{
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile,"vmload! " TARGET_FMT_lx "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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SVM_LOAD_SEG2(addr, segs[R_FS], fs);
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SVM_LOAD_SEG2(addr, segs[R_GS], gs);
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SVM_LOAD_SEG2(addr, tr, tr);
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SVM_LOAD_SEG2(addr, ldt, ldtr);
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#ifdef TARGET_X86_64
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env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb, save.kernel_gs_base));
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env->lstar = ldq_phys(addr + offsetof(struct vmcb, save.lstar));
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env->cstar = ldq_phys(addr + offsetof(struct vmcb, save.cstar));
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env->fmask = ldq_phys(addr + offsetof(struct vmcb, save.sfmask));
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#endif
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env->star = ldq_phys(addr + offsetof(struct vmcb, save.star));
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env->sysenter_cs = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_cs));
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env->sysenter_esp = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_esp));
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env->sysenter_eip = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_eip));
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}
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void helper_vmsave(target_ulong addr)
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{
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile,"vmsave! " TARGET_FMT_lx "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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SVM_SAVE_SEG(addr, segs[R_FS], fs);
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SVM_SAVE_SEG(addr, segs[R_GS], gs);
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SVM_SAVE_SEG(addr, tr, tr);
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SVM_SAVE_SEG(addr, ldt, ldtr);
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#ifdef TARGET_X86_64
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stq_phys(addr + offsetof(struct vmcb, save.kernel_gs_base), env->kernelgsbase);
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stq_phys(addr + offsetof(struct vmcb, save.lstar), env->lstar);
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stq_phys(addr + offsetof(struct vmcb, save.cstar), env->cstar);
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stq_phys(addr + offsetof(struct vmcb, save.sfmask), env->fmask);
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#endif
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stq_phys(addr + offsetof(struct vmcb, save.star), env->star);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_esp), env->sysenter_esp);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_eip), env->sysenter_eip);
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||||
}
|
||||
|
||||
void helper_skinit(void)
|
||||
{
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM)
|
||||
fprintf(logfile,"skinit!\n");
|
||||
}
|
||||
|
||||
void helper_invlpga(void)
|
||||
{
|
||||
tlb_flush(env, 0);
|
||||
}
|
||||
|
||||
int svm_check_intercept_param(uint32_t type, uint64_t param)
|
||||
{
|
||||
switch(type) {
|
||||
case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8:
|
||||
if (INTERCEPTEDw(_cr_read, (1 << (type - SVM_EXIT_READ_CR0)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 8:
|
||||
if (INTERCEPTEDw(_dr_read, (1 << (type - SVM_EXIT_READ_DR0)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8:
|
||||
if (INTERCEPTEDw(_cr_write, (1 << (type - SVM_EXIT_WRITE_CR0)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 8:
|
||||
if (INTERCEPTEDw(_dr_write, (1 << (type - SVM_EXIT_WRITE_DR0)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 16:
|
||||
if (INTERCEPTEDl(_exceptions, (1 << (type - SVM_EXIT_EXCP_BASE)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
case SVM_EXIT_IOIO:
|
||||
if (INTERCEPTED(1ULL << INTERCEPT_IOIO_PROT)) {
|
||||
/* FIXME: this should be read in at vmrun (faster this way?) */
|
||||
uint64_t addr = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.iopm_base_pa));
|
||||
uint16_t port = (uint16_t) (param >> 16);
|
||||
|
||||
if(ldub_phys(addr + port / 8) & (1 << (port % 8)))
|
||||
vmexit(type, param);
|
||||
}
|
||||
break;
|
||||
|
||||
case SVM_EXIT_MSR:
|
||||
if (INTERCEPTED(1ULL << INTERCEPT_MSR_PROT)) {
|
||||
/* FIXME: this should be read in at vmrun (faster this way?) */
|
||||
uint64_t addr = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.msrpm_base_pa));
|
||||
switch((uint32_t)ECX) {
|
||||
case 0 ... 0x1fff:
|
||||
T0 = (ECX * 2) % 8;
|
||||
T1 = ECX / 8;
|
||||
break;
|
||||
case 0xc0000000 ... 0xc0001fff:
|
||||
T0 = (8192 + ECX - 0xc0000000) * 2;
|
||||
T1 = (T0 / 8);
|
||||
T0 %= 8;
|
||||
break;
|
||||
case 0xc0010000 ... 0xc0011fff:
|
||||
T0 = (16384 + ECX - 0xc0010000) * 2;
|
||||
T1 = (T0 / 8);
|
||||
T0 %= 8;
|
||||
break;
|
||||
default:
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
if (ldub_phys(addr + T1) & ((1 << param) << T0))
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (INTERCEPTED((1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR)))) {
|
||||
vmexit(type, param);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void vmexit(uint64_t exit_code, uint64_t exit_info_1)
|
||||
{
|
||||
uint32_t int_ctl;
|
||||
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM)
|
||||
fprintf(logfile,"vmexit(%016" PRIx64 ", %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n",
|
||||
exit_code, exit_info_1,
|
||||
ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2)),
|
||||
EIP);
|
||||
|
||||
/* Save the VM state in the vmcb */
|
||||
SVM_SAVE_SEG(env->vm_vmcb, segs[R_ES], es);
|
||||
SVM_SAVE_SEG(env->vm_vmcb, segs[R_CS], cs);
|
||||
SVM_SAVE_SEG(env->vm_vmcb, segs[R_SS], ss);
|
||||
SVM_SAVE_SEG(env->vm_vmcb, segs[R_DS], ds);
|
||||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base), env->gdt.base);
|
||||
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit), env->gdt.limit);
|
||||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base), env->idt.base);
|
||||
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit), env->idt.limit);
|
||||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
|
||||
|
||||
if ((int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl))) & V_INTR_MASKING_MASK) {
|
||||
int_ctl &= ~V_TPR_MASK;
|
||||
int_ctl |= env->cr[8] & V_TPR_MASK;
|
||||
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
|
||||
}
|
||||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags), compute_eflags());
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip), env->eip);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), EAX);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
|
||||
stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl), env->hflags & HF_CPL_MASK);
|
||||
|
||||
/* Reload the host state from vm_hsave */
|
||||
env->hflags &= ~HF_HIF_MASK;
|
||||
env->intercept = 0;
|
||||
env->intercept_exceptions = 0;
|
||||
env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
|
||||
|
||||
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base));
|
||||
env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit));
|
||||
|
||||
env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base));
|
||||
env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit));
|
||||
|
||||
cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0)) | CR0_PE_MASK);
|
||||
cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4)));
|
||||
cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3)));
|
||||
if (int_ctl & V_INTR_MASKING_MASK)
|
||||
env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr8));
|
||||
/* we need to set the efer after the crs so the hidden flags get set properly */
|
||||
#ifdef TARGET_X86_64
|
||||
env->efer = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer));
|
||||
env->hflags &= ~HF_LMA_MASK;
|
||||
if (env->efer & MSR_EFER_LMA)
|
||||
env->hflags |= HF_LMA_MASK;
|
||||
#endif
|
||||
|
||||
env->eflags = 0;
|
||||
load_eflags(ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags)),
|
||||
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
||||
CC_OP = CC_OP_EFLAGS;
|
||||
|
||||
SVM_LOAD_SEG(env->vm_hsave, ES, es);
|
||||
SVM_LOAD_SEG(env->vm_hsave, CS, cs);
|
||||
SVM_LOAD_SEG(env->vm_hsave, SS, ss);
|
||||
SVM_LOAD_SEG(env->vm_hsave, DS, ds);
|
||||
|
||||
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
|
||||
ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
|
||||
EAX = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
|
||||
|
||||
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
|
||||
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
|
||||
|
||||
/* other setups */
|
||||
cpu_x86_set_cpl(env, 0);
|
||||
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_code_hi), (uint32_t)(exit_code >> 32));
|
||||
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_code), exit_code);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1), exit_info_1);
|
||||
|
||||
helper_clgi();
|
||||
/* FIXME: Resets the current ASID register to zero (host ASID). */
|
||||
|
||||
/* Clears the V_IRQ and V_INTR_MASKING bits inside the processor. */
|
||||
|
||||
/* Clears the TSC_OFFSET inside the processor. */
|
||||
|
||||
/* If the host is in PAE mode, the processor reloads the host's PDPEs
|
||||
from the page table indicated the host's CR3. If the PDPEs contain
|
||||
illegal state, the processor causes a shutdown. */
|
||||
|
||||
/* Forces CR0.PE = 1, RFLAGS.VM = 0. */
|
||||
env->cr[0] |= CR0_PE_MASK;
|
||||
env->eflags &= ~VM_MASK;
|
||||
|
||||
/* Disables all breakpoints in the host DR7 register. */
|
||||
|
||||
/* Checks the reloaded host state for consistency. */
|
||||
|
||||
/* If the host's rIP reloaded by #VMEXIT is outside the limit of the
|
||||
host's code segment or non-canonical (in the case of long mode), a
|
||||
#GP fault is delivered inside the host.) */
|
||||
|
||||
/* remove any pending exception */
|
||||
env->exception_index = -1;
|
||||
env->error_code = 0;
|
||||
env->old_exception = -1;
|
||||
|
||||
regs_to_env();
|
||||
cpu_loop_exit();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue