mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 23:33:54 -06:00
x86: avoid AREG0 for SVM helpers
Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
7923057bae
commit
052e80d5e0
4 changed files with 110 additions and 115 deletions
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@ -18,46 +18,46 @@
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*/
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "cpu-all.h"
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#include "helper.h"
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/* Secure Virtual Machine helpers */
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#if defined(CONFIG_USER_ONLY)
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void helper_vmrun(int aflag, int next_eip_addend)
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void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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{
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}
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void helper_vmmcall(void)
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void helper_vmmcall(CPUX86State *env)
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{
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}
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void helper_vmload(int aflag)
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void helper_vmload(CPUX86State *env, int aflag)
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{
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}
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void helper_vmsave(int aflag)
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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}
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void helper_stgi(void)
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void helper_stgi(CPUX86State *env)
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{
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}
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void helper_clgi(void)
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void helper_clgi(CPUX86State *env)
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{
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}
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void helper_skinit(void)
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void helper_skinit(CPUX86State *env)
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{
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}
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void helper_invlpga(int aflag)
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void helper_invlpga(CPUX86State *env, int aflag)
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{
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}
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void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
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void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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{
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}
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@ -65,7 +65,8 @@ void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1)
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{
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}
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void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
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void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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}
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@ -74,13 +75,13 @@ void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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{
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}
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void helper_svm_check_io(uint32_t port, uint32_t param,
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void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
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uint32_t next_eip_addend)
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{
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}
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#else
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static inline void svm_save_seg(target_phys_addr_t addr,
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static inline void svm_save_seg(CPUX86State *env, target_phys_addr_t addr,
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const SegmentCache *sc)
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{
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stw_phys(addr + offsetof(struct vmcb_seg, selector),
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@ -93,7 +94,8 @@ static inline void svm_save_seg(target_phys_addr_t addr,
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((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
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}
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static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc)
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static inline void svm_load_seg(CPUX86State *env, target_phys_addr_t addr,
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SegmentCache *sc)
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{
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unsigned int flags;
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@ -104,23 +106,23 @@ static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc)
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sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
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}
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static inline void svm_load_seg_cache(target_phys_addr_t addr,
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CPUX86State *env, int seg_reg)
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static inline void svm_load_seg_cache(CPUX86State *env, target_phys_addr_t addr,
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int seg_reg)
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{
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SegmentCache sc1, *sc = &sc1;
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svm_load_seg(addr, sc);
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svm_load_seg(env, addr, sc);
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cpu_x86_load_seg_cache(env, seg_reg, sc->selector,
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sc->base, sc->limit, sc->flags);
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}
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void helper_vmrun(int aflag, int next_eip_addend)
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void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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{
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target_ulong addr;
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uint32_t event_inj;
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uint32_t int_ctl;
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helper_svm_check_intercept_param(SVM_EXIT_VMRUN, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0);
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if (aflag == 2) {
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addr = EAX;
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@ -154,13 +156,13 @@ void helper_vmrun(int aflag, int next_eip_addend)
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags),
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cpu_compute_eflags(env));
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svm_save_seg(env->vm_hsave + offsetof(struct vmcb, save.es),
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es),
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&env->segs[R_ES]);
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svm_save_seg(env->vm_hsave + offsetof(struct vmcb, save.cs),
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
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&env->segs[R_CS]);
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svm_save_seg(env->vm_hsave + offsetof(struct vmcb, save.ss),
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
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&env->segs[R_SS]);
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svm_save_seg(env->vm_hsave + offsetof(struct vmcb, save.ds),
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
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&env->segs[R_DS]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
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@ -233,14 +235,14 @@ void helper_vmrun(int aflag, int next_eip_addend)
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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CC_OP = CC_OP_EFLAGS;
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svm_load_seg_cache(env->vm_vmcb + offsetof(struct vmcb, save.es),
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env, R_ES);
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svm_load_seg_cache(env->vm_vmcb + offsetof(struct vmcb, save.cs),
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env, R_CS);
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svm_load_seg_cache(env->vm_vmcb + offsetof(struct vmcb, save.ss),
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env, R_SS);
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svm_load_seg_cache(env->vm_vmcb + offsetof(struct vmcb, save.ds),
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env, R_DS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
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R_ES);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
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R_CS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
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R_SS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
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R_DS);
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EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
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env->eip = EIP;
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@ -320,17 +322,17 @@ void helper_vmrun(int aflag, int next_eip_addend)
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}
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}
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void helper_vmmcall(void)
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void helper_vmmcall(CPUX86State *env)
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{
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helper_svm_check_intercept_param(SVM_EXIT_VMMCALL, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMMCALL, 0);
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raise_exception(env, EXCP06_ILLOP);
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}
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void helper_vmload(int aflag)
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void helper_vmload(CPUX86State *env, int aflag)
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{
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target_ulong addr;
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helper_svm_check_intercept_param(SVM_EXIT_VMLOAD, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);
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if (aflag == 2) {
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addr = EAX;
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@ -340,17 +342,14 @@ void helper_vmload(int aflag)
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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addr, ldq_phys(addr + offsetof(struct vmcb,
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save.fs.base)),
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env->segs[R_FS].base);
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svm_load_seg_cache(addr + offsetof(struct vmcb, save.fs),
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env, R_FS);
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svm_load_seg_cache(addr + offsetof(struct vmcb, save.gs),
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env, R_GS);
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svm_load_seg(addr + offsetof(struct vmcb, save.tr),
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&env->tr);
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svm_load_seg(addr + offsetof(struct vmcb, save.ldtr),
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&env->ldt);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.fs), R_FS);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.gs), R_GS);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.tr), &env->tr);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
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#ifdef TARGET_X86_64
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env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb,
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@ -367,11 +366,11 @@ void helper_vmload(int aflag)
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save.sysenter_eip));
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}
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void helper_vmsave(int aflag)
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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target_ulong addr;
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helper_svm_check_intercept_param(SVM_EXIT_VMSAVE, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);
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if (aflag == 2) {
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addr = EAX;
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@ -384,13 +383,13 @@ void helper_vmsave(int aflag)
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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svm_save_seg(addr + offsetof(struct vmcb, save.fs),
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svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
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&env->segs[R_FS]);
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svm_save_seg(addr + offsetof(struct vmcb, save.gs),
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svm_save_seg(env, addr + offsetof(struct vmcb, save.gs),
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&env->segs[R_GS]);
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svm_save_seg(addr + offsetof(struct vmcb, save.tr),
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svm_save_seg(env, addr + offsetof(struct vmcb, save.tr),
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&env->tr);
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svm_save_seg(addr + offsetof(struct vmcb, save.ldtr),
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svm_save_seg(env, addr + offsetof(struct vmcb, save.ldtr),
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&env->ldt);
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#ifdef TARGET_X86_64
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@ -408,30 +407,30 @@ void helper_vmsave(int aflag)
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env->sysenter_eip);
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}
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void helper_stgi(void)
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void helper_stgi(CPUX86State *env)
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{
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helper_svm_check_intercept_param(SVM_EXIT_STGI, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0);
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env->hflags2 |= HF2_GIF_MASK;
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}
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void helper_clgi(void)
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void helper_clgi(CPUX86State *env)
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{
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helper_svm_check_intercept_param(SVM_EXIT_CLGI, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0);
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env->hflags2 &= ~HF2_GIF_MASK;
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}
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void helper_skinit(void)
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void helper_skinit(CPUX86State *env)
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{
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helper_svm_check_intercept_param(SVM_EXIT_SKINIT, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_SKINIT, 0);
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/* XXX: not implemented */
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raise_exception(env, EXCP06_ILLOP);
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}
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void helper_invlpga(int aflag)
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void helper_invlpga(CPUX86State *env, int aflag)
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{
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target_ulong addr;
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helper_svm_check_intercept_param(SVM_EXIT_INVLPGA, 0);
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cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
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if (aflag == 2) {
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addr = EAX;
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@ -444,7 +443,8 @@ void helper_invlpga(int aflag)
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tlb_flush_page(env, addr);
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}
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void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
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void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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if (likely(!(env->hflags & HF_SVMI_MASK))) {
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return;
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@ -452,27 +452,27 @@ void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
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switch (type) {
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case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8:
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if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8:
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if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7:
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if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7:
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if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31:
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if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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case SVM_EXIT_MSR:
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@ -499,36 +499,31 @@ void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
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t0 %= 8;
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break;
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default:
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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t0 = 0;
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t1 = 0;
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break;
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}
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if (ldub_phys(addr + t1) & ((1 << param) << t0)) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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}
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break;
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default:
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if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) {
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helper_vmexit(type, param);
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helper_vmexit(env, type, param);
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}
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break;
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}
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}
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void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
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void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = env1;
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helper_svm_check_intercept_param(type, param);
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env = saved_env;
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helper_svm_check_intercept_param(env, type, param);
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}
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void helper_svm_check_io(uint32_t port, uint32_t param,
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void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
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uint32_t next_eip_addend)
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{
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if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
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@ -541,13 +536,13 @@ void helper_svm_check_io(uint32_t port, uint32_t param,
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/* next EIP */
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stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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env->eip + next_eip_addend);
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helper_vmexit(SVM_EXIT_IOIO, param | (port << 16));
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helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16));
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}
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}
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}
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/* Note: currently only 32 bits of exit_code are used */
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void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
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void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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{
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uint32_t int_ctl;
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@ -567,13 +562,13 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
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}
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/* Save the VM state in the vmcb */
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svm_save_seg(env->vm_vmcb + offsetof(struct vmcb, save.es),
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
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&env->segs[R_ES]);
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svm_save_seg(env->vm_vmcb + offsetof(struct vmcb, save.cs),
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
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&env->segs[R_CS]);
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svm_save_seg(env->vm_vmcb + offsetof(struct vmcb, save.ss),
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
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&env->segs[R_SS]);
|
||||
svm_save_seg(env->vm_vmcb + offsetof(struct vmcb, save.ds),
|
||||
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
|
||||
&env->segs[R_DS]);
|
||||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
|
||||
|
|
@ -602,7 +597,8 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
|
|||
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags),
|
||||
cpu_compute_eflags(env));
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip), env->eip);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
|
||||
env->eip);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), EAX);
|
||||
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
|
||||
|
|
@ -645,14 +641,14 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
|
|||
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
||||
CC_OP = CC_OP_EFLAGS;
|
||||
|
||||
svm_load_seg_cache(env->vm_hsave + offsetof(struct vmcb, save.es),
|
||||
env, R_ES);
|
||||
svm_load_seg_cache(env->vm_hsave + offsetof(struct vmcb, save.cs),
|
||||
env, R_CS);
|
||||
svm_load_seg_cache(env->vm_hsave + offsetof(struct vmcb, save.ss),
|
||||
env, R_SS);
|
||||
svm_load_seg_cache(env->vm_hsave + offsetof(struct vmcb, save.ds),
|
||||
env, R_DS);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.es),
|
||||
R_ES);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
|
||||
R_CS);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
|
||||
R_SS);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
|
||||
R_DS);
|
||||
|
||||
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
|
||||
ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
|
||||
|
|
@ -707,10 +703,9 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
|
|||
cpu_loop_exit(env);
|
||||
}
|
||||
|
||||
void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1)
|
||||
void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
||||
{
|
||||
env = nenv;
|
||||
helper_vmexit(exit_code, exit_info_1);
|
||||
helper_vmexit(env, exit_code, exit_info_1);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue