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First RISC-V PR for QEMU 8.0

Browse source 
* Fix PMP propagation for tlb
 * Collection of bug fixes
 * Bump the OpenTitan supported version
 * Add smstateen support
 * Support native debug icount trigger
 * Remove the redundant ipi-id property in the virt machine
 * Support cache-related PMU events in virtual mode
 * Add some missing PolarFire SoC io regions
 * Fix mret exception cause when no pmp rule is configured
 * Fix bug where disabling compressed instructions would crash QEMU
 * Add Zawrs ISA extension support
 * A range of code refactoring and cleanups
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Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

# gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits)
  hw/intc: sifive_plic: Fix the pending register range check
  hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
  hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
  hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
  hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
  hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
  hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
  hw/intc: sifive_plic: Update "num-sources" property default value
  hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
  hw/intc: sifive_plic: Improve robustness of the PLIC config parser
  hw/intc: sifive_plic: Drop PLICMode_H
  hw/riscv: spike: Remove misleading comments
  hw/riscv: Sort machines Kconfig options in alphabetical order
  hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
  hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
  hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
  RISC-V: Add Zawrs ISA extension support
  target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
  target/riscv: Simplify helper_sret() a little bit
  target/riscv: Set pc_succ_insn for !rvc illegal insn
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-06 22:15:53 +00:00
commit 052e6534c4
41 changed files with 1226 additions and 255 deletions
Download patch file Download diff file Expand all files Collapse all files

11
target/riscv/cpu.c
View file

@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@ -382,6 +383,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CSR_MHARTID,
CSR_MSTATUS,
CSR_MSTATUSH,
/*
* CSR_SSTATUS is intentionally omitted here as its value
* can be figured out by looking at CSR_MSTATUS
*/
CSR_HSTATUS,
CSR_VSSTATUS,
CSR_MIP,
@ -762,6 +767,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
@ -1017,6 +1027,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),

10
target/riscv/cpu.h
View file

@ -329,6 +329,9 @@ struct CPUArchState {
target_ulong tdata3[RV_MAX_TRIGGERS];
struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
int64_t last_icount;
bool itrigger_enabled;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void *);
@ -366,6 +369,9 @@ struct CPUArchState {
/* CSRs for execution enviornment configuration */
uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
target_ulong senvcfg;
uint64_t henvcfg;
#endif
@ -441,11 +447,13 @@ struct RISCVCPUConfig {
bool ext_ifencei;
bool ext_icsr;
bool ext_zihintpause;
bool ext_smstateen;
bool ext_sstc;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
bool ext_zdinx;
bool ext_zawrs;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zfinx;
@ -621,6 +629,8 @@ FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
FIELD(TB_FLAGS, VTA, 24, 1)
FIELD(TB_FLAGS, VMA, 25, 1)
/* Native debug itrigger */
FIELD(TB_FLAGS, ITRIGGER, 26, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)

37
target/riscv/cpu_bits.h
View file

@ -197,6 +197,12 @@
/* Supervisor Configuration CSRs */
#define CSR_SENVCFG 0x10A
/* Supervisor state CSRs */
#define CSR_SSTATEEN0 0x10C
#define CSR_SSTATEEN1 0x10D
#define CSR_SSTATEEN2 0x10E
#define CSR_SSTATEEN3 0x10F
/* Supervisor Trap Handling */
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@ -244,6 +250,16 @@
#define CSR_HENVCFG 0x60A
#define CSR_HENVCFGH 0x61A
/* Hypervisor state CSRs */
#define CSR_HSTATEEN0 0x60C
#define CSR_HSTATEEN0H 0x61C
#define CSR_HSTATEEN1 0x60D
#define CSR_HSTATEEN1H 0x61D
#define CSR_HSTATEEN2 0x60E
#define CSR_HSTATEEN2H 0x61E
#define CSR_HSTATEEN3 0x60F
#define CSR_HSTATEEN3H 0x61F
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
@ -289,6 +305,27 @@
#define CSR_MENVCFG 0x30A
#define CSR_MENVCFGH 0x31A
/* Machine state CSRs */
#define CSR_MSTATEEN0 0x30C
#define CSR_MSTATEEN0H 0x31C
#define CSR_MSTATEEN1 0x30D
#define CSR_MSTATEEN1H 0x31D
#define CSR_MSTATEEN2 0x30E
#define CSR_MSTATEEN2H 0x31E
#define CSR_MSTATEEN3 0x30F
#define CSR_MSTATEEN3H 0x31F
/* Common defines for all smstateen */
#define SMSTATEEN_MAX_COUNT 4
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)
#define SMSTATEEN0_SVSLCT (1ULL << 60)
#define SMSTATEEN0_HSENVCFG (1ULL << 62)
#define SMSTATEEN_STATEEN (1ULL << 63)
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH 0x757

26
target/riscv/cpu_helper.c
View file

@ -27,7 +27,9 @@
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
#include "sysemu/cpu-timers.h"
#include "cpu_bits.h"
#include "debug.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@ -103,6 +105,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
get_field(env->mstatus_hs, MSTATUS_VS));
}
if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
}
#endif
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
@ -662,6 +667,9 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
if (newpriv == PRV_H) {
newpriv = PRV_U;
}
if (icount_enabled() && newpriv != env->priv) {
riscv_itrigger_update_priv(env);
}
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
env->xl = cpu_recompute_xl(env);
@ -698,24 +706,26 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
int mode)
{
pmp_priv_t pmp_priv;
target_ulong tlb_size_pmp = 0;
int pmp_index = -1;
if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
mode)) {
pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
&pmp_priv, mode);
if (pmp_index < 0) {
*prot = 0;
return TRANSLATE_PMP_FAIL;
}
*prot = pmp_priv_to_page_prot(pmp_priv);
if (tlb_size != NULL) {
if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
*tlb_size = tlb_size_pmp;
}
if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
*tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
}
return TRANSLATE_SUCCESS;
@ -1240,6 +1250,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
}
pmu_tlb_fill_incr_ctr(cpu, access_type);
if (riscv_cpu_virt_enabled(env) ||
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
@ -1303,7 +1314,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
}
} else {
pmu_tlb_fill_incr_ctr(cpu, access_type);
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
access_type, mmu_idx, true, false, false);

393
target/riscv/csr.c
View file

@ -41,6 +41,42 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
}
/* Predicates */
#if !defined(CONFIG_USER_ONLY)
static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
uint64_t bit)
{
bool virt = riscv_cpu_virt_enabled(env);
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
return RISCV_EXCP_NONE;
}
if (!(env->mstateen[index] & bit)) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (virt) {
if (!(env->hstateen[index] & bit)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
if (!(env->sstateen[index] & bit)) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
return RISCV_EXCP_NONE;
}
#endif
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@ -283,6 +319,72 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
return umode(env, csrno);
}
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
return any(env, csrno);
}
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (env->priv < PRV_M) {
if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
return hmode(env, csrno);
}
static RISCVException hstateen(CPURISCVState *env, int csrno)
{
return hstateen_pred(env, csrno, CSR_HSTATEEN0);
}
static RISCVException hstateenh(CPURISCVState *env, int csrno)
{
return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
}
static RISCVException sstateen(CPURISCVState *env, int csrno)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (env->priv < PRV_M) {
if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (virt) {
if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
}
return smode(env, csrno);
}
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
@ -838,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
if (riscv_cpu_virt_enabled(env)) {
if (!(get_field(env->hcounteren, COUNTEREN_TM) &
if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
@ -1808,6 +1910,13 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
*val = env->senvcfg;
return RISCV_EXCP_NONE;
}
@ -1816,15 +1925,27 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
*val = env->henvcfg;
return RISCV_EXCP_NONE;
}
@ -1833,6 +1954,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= HENVCFG_PBMTE | HENVCFG_STCE;
@ -1846,6 +1973,13 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
*val = env->henvcfg >> 32;
return RISCV_EXCP_NONE;
}
@ -1855,12 +1989,208 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
{
uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
return RISCV_EXCP_NONE;
}
static RISCVException read_mstateen(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->mstateen[csrno - CSR_MSTATEEN0];
return RISCV_EXCP_NONE;
}
static RISCVException write_mstateen(CPURISCVState *env, int csrno,
uint64_t wr_mask, target_ulong new_val)
{
uint64_t *reg;
reg = &env->mstateen[csrno - CSR_MSTATEEN0];
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
return RISCV_EXCP_NONE;
}
static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
return write_mstateen(env, csrno, wr_mask, new_val);
}
static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
target_ulong new_val)
{
return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
return RISCV_EXCP_NONE;
}
static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
uint64_t wr_mask, target_ulong new_val)
{
uint64_t *reg, val;
reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
val = (uint64_t)new_val << 32;
val |= *reg & 0xFFFFFFFF;
*reg = (*reg & ~wr_mask) | (val & wr_mask);
return RISCV_EXCP_NONE;
}
static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
return write_mstateenh(env, csrno, wr_mask, new_val);
}
static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
target_ulong new_val)
{
return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException read_hstateen(CPURISCVState *env, int csrno,
target_ulong *val)
{
int index = csrno - CSR_HSTATEEN0;
*val = env->hstateen[index] & env->mstateen[index];
return RISCV_EXCP_NONE;
}
static RISCVException write_hstateen(CPURISCVState *env, int csrno,
uint64_t mask, target_ulong new_val)
{
int index = csrno - CSR_HSTATEEN0;
uint64_t *reg, wr_mask;
reg = &env->hstateen[index];
wr_mask = env->mstateen[index] & mask;
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
return RISCV_EXCP_NONE;
}
static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
return write_hstateen(env, csrno, wr_mask, new_val);
}
static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
target_ulong new_val)
{
return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
target_ulong *val)
{
int index = csrno - CSR_HSTATEEN0H;
*val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
return RISCV_EXCP_NONE;
}
static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
uint64_t mask, target_ulong new_val)
{
int index = csrno - CSR_HSTATEEN0H;
uint64_t *reg, wr_mask, val;
reg = &env->hstateen[index];
val = (uint64_t)new_val << 32;
val |= *reg & 0xFFFFFFFF;
wr_mask = env->mstateen[index] & mask;
*reg = (*reg & ~wr_mask) | (val & wr_mask);
return RISCV_EXCP_NONE;
}
static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
return write_hstateenh(env, csrno, wr_mask, new_val);
}
static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
target_ulong new_val)
{
return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException read_sstateen(CPURISCVState *env, int csrno,
target_ulong *val)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
*val = env->sstateen[index] & env->mstateen[index];
if (virt) {
*val &= env->hstateen[index];
}
return RISCV_EXCP_NONE;
}
static RISCVException write_sstateen(CPURISCVState *env, int csrno,
uint64_t mask, target_ulong new_val)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
uint64_t wr_mask;
uint64_t *reg;
wr_mask = env->mstateen[index] & mask;
if (virt) {
wr_mask &= env->hstateen[index];
}
reg = &env->sstateen[index];
*reg = (*reg & ~wr_mask) | (new_val & wr_mask);
return RISCV_EXCP_NONE;
}
static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
return write_sstateen(env, csrno, wr_mask, new_val);
}
static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
target_ulong new_val)
{
return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
@ -3744,6 +4074,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Smstateen extension CSRs */
[CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
write_mstateen0h,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
write_mstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
write_mstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
write_mstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
write_mstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
write_mstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
write_mstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
write_hstateen0h,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
write_hstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
write_hstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
write_hstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
write_hstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
write_hstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
write_hstateenh_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
write_sstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
write_sstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
write_sstateen_1_3,
.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
NULL, read_sstatus_i128 },

207
target/riscv/debug.c
View file

@ -29,6 +29,8 @@
#include "cpu.h"
#include "trace.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "sysemu/cpu-timers.h"
/*
* The following M-mode trigger CSRs are implemented:
@ -496,10 +498,209 @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
return;
}
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
/* icount trigger type */
static inline int
itrigger_get_count(CPURISCVState *env, int index)
{
return get_field(env->tdata1[index], ITRIGGER_COUNT);
}
static inline void
itrigger_set_count(CPURISCVState *env, int index, int value)
{
env->tdata1[index] = set_field(env->tdata1[index],
ITRIGGER_COUNT, value);
}
static bool check_itrigger_priv(CPURISCVState *env, int index)
{
target_ulong tdata1 = env->tdata1[index];
if (riscv_cpu_virt_enabled(env)) {
/* check VU/VS bit against current privilege level */
return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
(get_field(tdata1, ITRIGGER_VU) == env->priv);
} else {
/* check U/S/M bit against current privilege level */
return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
(get_field(tdata1, ITRIGGER_S) == env->priv) ||
(get_field(tdata1, ITRIGGER_U) == env->priv);
}
}
bool riscv_itrigger_enabled(CPURISCVState *env)
{
int count;
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
continue;
}
if (check_itrigger_priv(env, i)) {
continue;
}
count = itrigger_get_count(env, i);
if (!count) {
continue;
}
return true;
}
return false;
}
void helper_itrigger_match(CPURISCVState *env)
{
int count;
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
continue;
}
if (check_itrigger_priv(env, i)) {
continue;
}
count = itrigger_get_count(env, i);
if (!count) {
continue;
}
itrigger_set_count(env, i, count--);
if (!count) {
env->itrigger_enabled = riscv_itrigger_enabled(env);
do_trigger_action(env, i);
}
}
}
static void riscv_itrigger_update_count(CPURISCVState *env)
{
int count, executed;
/*
* Record last icount, so that we can evaluate the executed instructions
* since last priviledge mode change or timer expire.
*/
int64_t last_icount = env->last_icount, current_icount;
current_icount = env->last_icount = icount_get_raw();
for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
continue;
}
count = itrigger_get_count(env, i);
if (!count) {
continue;
}
/*
* Only when priviledge is changed or itrigger timer expires,
* the count field in itrigger tdata1 register is updated.
* And the count field in itrigger only contains remaining value.
*/
if (check_itrigger_priv(env, i)) {
/*
* If itrigger enabled in this priviledge mode, the number of
* executed instructions since last priviledge change
* should be reduced from current itrigger count.
*/
executed = current_icount - last_icount;
itrigger_set_count(env, i, count - executed);
if (count == executed) {
do_trigger_action(env, i);
}
} else {
/*
* If itrigger is not enabled in this priviledge mode,
* the number of executed instructions will be discard and
* the count field in itrigger will not change.
*/
timer_mod(env->itrigger_timer[i],
current_icount + count);
}
}
}
static void riscv_itrigger_timer_cb(void *opaque)
{
riscv_itrigger_update_count((CPURISCVState *)opaque);
}
void riscv_itrigger_update_priv(CPURISCVState *env)
{
riscv_itrigger_update_count(env);
}
static target_ulong itrigger_validate(CPURISCVState *env,
target_ulong ctrl)
{
target_ulong val;
/* validate the generic part first */
val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
/* validate unimplemented (always zero) bits */
warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
/* keep the mode and attribute bits */
val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
ITRIGGER_M | ITRIGGER_COUNT);
return val;
}
static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
int tdata_index, target_ulong val)
{
target_ulong new_val;
switch (tdata_index) {
case TDATA1:
/* set timer for icount */
new_val = itrigger_validate(env, val);
if (new_val != env->tdata1[index]) {
env->tdata1[index] = new_val;
if (icount_enabled()) {
env->last_icount = icount_get_raw();
/* set the count to timer */
timer_mod(env->itrigger_timer[index],
env->last_icount + itrigger_get_count(env, index));
} else {
env->itrigger_enabled = riscv_itrigger_enabled(env);
}
}
break;
case TDATA2:
qemu_log_mask(LOG_UNIMP,
"tdata2 is not supported for icount trigger\n");
break;
case TDATA3:
qemu_log_mask(LOG_UNIMP,
"tdata3 is not supported for icount trigger\n");
break;
default:
g_assert_not_reached();
}
return;
}
static int itrigger_get_adjust_count(CPURISCVState *env)
{
int count = itrigger_get_count(env, env->trigger_cur), executed;
if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
executed = icount_get_raw() - env->last_icount;
count += executed;
}
return count;
}
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
{
int trigger_type;
switch (tdata_index) {
case TDATA1:
trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
itrigger_get_adjust_count(env));
}
return env->tdata1[env->trigger_cur];
case TDATA2:
return env->tdata2[env->trigger_cur];
@ -528,6 +729,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
type6_reg_write(env, env->trigger_cur, tdata_index, val);
break;
case TRIGGER_TYPE_INST_CNT:
itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
break;
case TRIGGER_TYPE_INT:
case TRIGGER_TYPE_EXCP:
case TRIGGER_TYPE_EXT_SRC:
@ -725,5 +928,7 @@ void riscv_trigger_init(CPURISCVState *env)
env->tdata3[i] = 0;
env->cpu_breakpoint[i] = NULL;
env->cpu_watchpoint[i] = NULL;
env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
riscv_itrigger_timer_cb, env);
}
}

13
target/riscv/debug.h
View file

@ -118,6 +118,17 @@ enum {
SIZE_NUM = 16
};
/* itrigger filed masks */
#define ITRIGGER_ACTION 0x3f
#define ITRIGGER_U BIT(6)
#define ITRIGGER_S BIT(7)
#define ITRIGGER_PENDING BIT(8)
#define ITRIGGER_M BIT(9)
#define ITRIGGER_COUNT (0x3fff << 10)
#define ITRIGGER_HIT BIT(24)
#define ITRIGGER_VU BIT(25)
#define ITRIGGER_VS BIT(26)
bool tdata_available(CPURISCVState *env, int tdata_index);
target_ulong tselect_csr_read(CPURISCVState *env);
@ -134,4 +145,6 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
void riscv_trigger_init(CPURISCVState *env);
bool riscv_itrigger_enabled(CPURISCVState *env);
void riscv_itrigger_update_priv(CPURISCVState *env);
#endif /* RISCV_DEBUG_H */

2
target/riscv/helper.h
View file

@ -109,6 +109,8 @@ DEF_HELPER_1(sret, tl, env)
DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
/* Native Debug */
DEF_HELPER_1(itrigger_match, void, env)
#endif
/* Hypervisor functions */

4
target/riscv/insn32.decode
View file

@ -718,6 +718,10 @@ vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** Zawrs Standard Extension ***
wrs_nto 000000001101 00000 000 00000 1110011
wrs_sto 000000011101 00000 000 00000 1110011
# *** RV32 Zba Standard Extension ***
sh1add 0010000 .......... 010 ..... 0110011 @r
sh2add 0010000 .......... 100 ..... 0110011 @r

4
target/riscv/insn_trans/trans_privileged.c.inc
View file

@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
if (has_ext(ctx, RVS)) {
decode_save_opc(ctx);
gen_helper_sret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
return false;
@ -94,7 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
gen_helper_mret(cpu_pc, cpu_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#else

8
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -66,7 +66,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
}
gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
lookup_and_goto_ptr(ctx);
if (misaligned) {
gen_set_label(misaligned);
@ -803,7 +803,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
* end the TB and return to main loop
*/
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
tcg_gen_exit_tb(NULL, 0);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
@ -827,7 +827,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
* however we need to end the translation block
*/
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
tcg_gen_exit_tb(NULL, 0);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
@ -838,7 +838,7 @@ static bool do_csr_post(DisasContext *ctx)
decode_save_opc(ctx);
/* We may have changed important cpu state -- exit to main loop. */
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
tcg_gen_exit_tb(NULL, 0);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}

4
target/riscv/insn_trans/trans_rvv.c.inc
View file

@ -196,7 +196,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
mark_vs_dirty(s);
gen_set_pc_imm(s, s->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
if (rd == 0 && rs1 == 0) {
@ -222,7 +222,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
gen_set_pc_imm(s, s->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
return true;

51
target/riscv/insn_trans/trans_rvzawrs.c.inc Normal file
View file

@ -0,0 +1,51 @@
/*
* RISC-V translation routines for the RISC-V Zawrs Extension.
*
* Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_wrs(DisasContext *ctx)
{
if (!ctx->cfg_ptr->ext_zawrs) {
return false;
}
/*
* The specification says:
* While stalled, an implementation is permitted to occasionally
* terminate the stall and complete execution for any reason.
*
* So let's just exit TB and return to the main loop.
*/
/* Clear the load reservation (if any). */
tcg_gen_movi_tl(load_res, -1);
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
#define GEN_TRANS_WRS(insn) \
static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
{ \
(void)a; \
return trans_wrs(ctx); \
}
GEN_TRANS_WRS(wrs_nto)
GEN_TRANS_WRS(wrs_sto)

36
target/riscv/machine.c
View file

@ -21,6 +21,8 @@
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "migration/cpu.h"
#include "sysemu/cpu-timers.h"
#include "debug.h"
static bool pmp_needed(void *opaque)
{
@ -229,11 +231,24 @@ static bool debug_needed(void *opaque)
return riscv_feature(env, RISCV_FEATURE_DEBUG);
}
static int debug_post_load(void *opaque, int version_id)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
if (icount_enabled()) {
env->itrigger_enabled = riscv_itrigger_enabled(env);
}
return 0;
}
static const VMStateDescription vmstate_debug = {
.name = "cpu/debug",
.version_id = 2,
.minimum_version_id = 2,
.needed = debug_needed,
.post_load = debug_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
@ -253,6 +268,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
return 0;
}
static bool smstateen_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
return cpu->cfg.ext_smstateen;
}
static const VMStateDescription vmstate_smstateen = {
.name = "cpu/smtateen",
.version_id = 1,
.minimum_version_id = 1,
.needed = smstateen_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
VMSTATE_END_OF_LIST()
}
};
static bool envcfg_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
@ -364,6 +399,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_kvmtimer,
&vmstate_envcfg,
&vmstate_debug,
&vmstate_smstateen,
NULL
}
};

28
target/riscv/op_helper.c
View file

@ -149,21 +149,24 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = env->mstatus;
prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus, MSTATUS_SIE,
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
if (env->priv_ver >= PRIV_VERSION_1_12_0) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
env->mstatus = mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
/* We support Hypervisor extensions and virtulisation is disabled */
target_ulong hstatus = env->hstatus;
prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
hstatus = set_field(hstatus, HSTATUS_SPV, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, 0);
mstatus = set_field(mstatus, SSTATUS_SIE,
get_field(mstatus, SSTATUS_SPIE));
mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
env->mstatus = mstatus;
env->hstatus = hstatus;
if (prev_virt) {
@ -171,14 +174,6 @@ target_ulong helper_sret(CPURISCVState *env)
}
riscv_cpu_set_virt_enabled(env, prev_virt);
} else {
prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus, MSTATUS_SIE,
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
env->mstatus = mstatus;
}
riscv_cpu_set_mode(env, prev_priv);
@ -202,7 +197,7 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
@ -211,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
}
env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);

90
target/riscv/pmp.c
View file

@ -292,8 +292,11 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
/*
* Check if the address has required RWX privs to complete desired operation
* Return PMP rule index if a pmp rule match
* Return MAX_RISCV_PMPS if default match
* Return negtive value if no match
*/
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
target_ulong mode)
{
@ -305,8 +308,10 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
return pmp_hart_has_privs_default(env, addr, size, privs,
allowed_privs, mode);
if (pmp_hart_has_privs_default(env, addr, size, privs,
allowed_privs, mode)) {
ret = MAX_RISCV_PMPS;
}
}
if (size == 0) {
@ -333,7 +338,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
ret = 0;
ret = -1;
break;
}
@ -436,18 +441,22 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
}
}
ret = ((privs & *allowed_privs) == privs);
if ((privs & *allowed_privs) == privs) {
ret = i;
}
break;
}
}
/* No rule matched */
if (ret == -1) {
return pmp_hart_has_privs_default(env, addr, size, privs,
allowed_privs, mode);
if (pmp_hart_has_privs_default(env, addr, size, privs,
allowed_privs, mode)) {
ret = MAX_RISCV_PMPS;
}
}
return ret == 1 ? true : false;
return ret;
}
/*
@ -586,64 +595,25 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
* Calculate the TLB size if the start address or the end address of
* PMP entry is presented in the TLB page.
*/
static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea)
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea)
{
target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
return pmp_ea - pmp_sa + 1;
}
if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
return tlb_ea - pmp_sa + 1;
}
if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
return pmp_ea - tlb_sa + 1;
}
return 0;
}
/*
* Check is there a PMP entry which range covers this page. If so,
* try to find the minimum granularity for the TLB size.
*/
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size)
{
int i;
target_ulong val;
target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
for (i = 0; i < MAX_RISCV_PMPS; i++) {
val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
if (val) {
if (*tlb_size == 0 || *tlb_size > val) {
*tlb_size = val;
}
}
}
if (*tlb_size != 0) {
if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
return TARGET_PAGE_SIZE;
} else {
/*
* At this point we have a tlb_size that is the smallest possible size
* That fits within a TARGET_PAGE_SIZE and the PMP region.
*
* If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
* This means the result isn't cached in the TLB and is only used for
* a single translation.
*/
if (*tlb_size < TARGET_PAGE_SIZE) {
*tlb_size = 1;
}
return true;
* At this point we have a tlb_size that is the smallest possible size
* That fits within a TARGET_PAGE_SIZE and the PMP region.
*
* If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
* This means the result isn't cached in the TLB and is only used for
* a single translation.
*/
return 1;
}
return false;
}
/*

6
target/riscv/pmp.h
View file

@ -72,11 +72,11 @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
target_ulong mode);
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
target_ulong tlb_sa, target_ulong tlb_ea);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
uint32_t pmp_get_num_rules(CPURISCVState *env);

54
target/riscv/translate.c
View file

@ -76,6 +76,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
RISCVMXL ol;
bool virt_inst_excp;
bool virt_enabled;
const RISCVCPUConfig *cfg_ptr;
bool hlsx;
@ -111,6 +112,8 @@ typedef struct DisasContext {
/* PointerMasking extension */
bool pm_mask_enabled;
bool pm_base_enabled;
/* Use icount trigger for native debug */
bool itrigger;
/* TCG of the current insn_start */
TCGOp *insn_start;
} DisasContext;
@ -243,7 +246,11 @@ static void gen_exception_illegal(DisasContext *ctx)
{
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
offsetof(CPURISCVState, bins));
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
if (ctx->virt_inst_excp) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
}
static void gen_exception_inst_addr_mis(DisasContext *ctx)
@ -252,15 +259,39 @@ static void gen_exception_inst_addr_mis(DisasContext *ctx)
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
static void lookup_and_goto_ptr(DisasContext *ctx)
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
gen_helper_itrigger_match(cpu_env);
}
#endif
tcg_gen_lookup_and_goto_ptr();
}
static void exit_tb(DisasContext *ctx)
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
gen_helper_itrigger_match(cpu_env);
}
#endif
tcg_gen_exit_tb(NULL, 0);
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
/*
* Under itrigger, instruction executes one by one like singlestep,
* direct block chain benefits will be small.
*/
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
tcg_gen_goto_tb(n);
gen_set_pc_imm(ctx, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
gen_set_pc_imm(ctx, dest);
tcg_gen_lookup_and_goto_ptr();
lookup_and_goto_ptr(ctx);
}
}
@ -1029,6 +1060,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
@ -1062,16 +1094,13 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps },
};
ctx->virt_inst_excp = false;
/* Check for compressed insn */
if (insn_len(opcode) == 2) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (decode_insn16(ctx, opcode)) {
return;
}
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
return;
}
} else {
uint32_t opcode32 = opcode;
@ -1136,6 +1165,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
}
@ -1175,7 +1205,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
if (!is_same_page(&ctx->base, ctx->base.pc_next)) {
if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
} else {
unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;