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ppc4xx_sdram: Drop extra zeros for readability

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Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <93974622c3d398c7d3a3488b678b74c3807849de.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-09-24 14:27:57 +02:00 • committed by Daniel Henrique Barboza
parent 4fc30e153a
commit 052ae5dcc0
1 changed files with 20 additions and 20 deletions
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40
hw/ppc/ppc4xx_devs.c
View file

@ -54,31 +54,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
switch (ram_size) { switch (ram_size) {
case 4 * MiB: case 4 * MiB:
bcr = 0x00000000; bcr = 0;
break; break;
case 8 * MiB: case 8 * MiB:
bcr = 0x00020000; bcr = 0x20000;
break; break;
case 16 * MiB: case 16 * MiB:
bcr = 0x00040000; bcr = 0x40000;
break; break;
case 32 * MiB: case 32 * MiB:
bcr = 0x00060000; bcr = 0x60000;
break; break;
case 64 * MiB: case 64 * MiB:
bcr = 0x00080000; bcr = 0x80000;
break; break;
case 128 * MiB: case 128 * MiB:
bcr = 0x000A0000; bcr = 0xA0000;
break; break;
case 256 * MiB: case 256 * MiB:
bcr = 0x000C0000; bcr = 0xC0000;
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__, "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
ram_size); ram_size);
return 0x00000000; return 0;
} }
bcr |= ram_base & 0xFF800000; bcr |= ram_base & 0xFF800000;
bcr |= 1; bcr |= 1;
@ -109,7 +109,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i, static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled) uint32_t bcr, int enabled)
{ {
if (sdram->bank[i].bcr & 0x00000001) { if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */ /* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr)); sdram_size(sdram->bank[i].bcr));
@ -120,7 +120,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
object_unparent(OBJECT(&sdram->bank[i].container)); object_unparent(OBJECT(&sdram->bank[i].container));
} }
sdram->bank[i].bcr = bcr & 0xFFDEE001; sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) { if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container", memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr)); sdram_size(bcr));
@ -141,7 +141,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base, sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1); sdram->bank[i].size), 1);
} else { } else {
sdram_set_bcr(sdram, i, 0x00000000, 0); sdram_set_bcr(sdram, i, 0, 0);
} }
} }
} }
@ -218,7 +218,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
break; break;
default: default:
/* Avoid gcc warning */ /* Avoid gcc warning */
ret = 0x00000000; ret = 0;
break; break;
} }
@ -311,18 +311,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{ {
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev); Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
sdram->addr = 0x00000000; sdram->addr = 0;
sdram->bear = 0x00000000; sdram->bear = 0;
sdram->besr0 = 0x00000000; /* No error */ sdram->besr0 = 0; /* No error */
sdram->besr1 = 0x00000000; /* No error */ sdram->besr1 = 0; /* No error */
sdram->cfg = 0x00000000; sdram->cfg = 0;
sdram->ecccfg = 0x00000000; /* No ECC */ sdram->ecccfg = 0; /* No ECC */
sdram->eccesr = 0x00000000; /* No error */ sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C00000; sdram->pmit = 0x07C00000;
sdram->rtr = 0x05F00000; sdram->rtr = 0x05F00000;
sdram->tr = 0x00854009; sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */ /* We pre-initialize RAM banks */
sdram->status = 0x00000000; sdram->status = 0;
sdram->cfg = 0x00800000; sdram->cfg = 0x00800000;
} }