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target/mips: Update ITU to utilize SAARI and SAAR CP0 registers

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Update ITU to utilize SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2019-01-03 16:46:32 +01:00 • committed by Aleksandar Markovic
parent e5345d9675
commit 043715d1e0
5 changed files with 54 additions and 6 deletions
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4
include/hw/misc/mips_itu.h
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@ -70,6 +70,10 @@ typedef struct MIPSITUState {
/* ITU Control Register */
uint64_t icr0;
/* SAAR */
bool saar_present;
void *saar;
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */