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target/openrisc: Convert to 3-phase reset

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Convert the openrisc CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20221124115023.2437291-13-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:15 +00:00
parent 4245a71662
commit 0409750479
2 changed files with 10 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

12
target/openrisc/cpu.c
View file

@ -70,13 +70,15 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
info->print_insn = print_insn_or1k; info->print_insn = print_insn_or1k;
} }
static void openrisc_cpu_reset(DeviceState *dev) static void openrisc_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(dev); CPUState *s = CPU(obj);
OpenRISCCPU *cpu = OPENRISC_CPU(s); OpenRISCCPU *cpu = OPENRISC_CPU(s);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
occ->parent_reset(dev); if (occ->parent_phases.hold) {
occ->parent_phases.hold(obj);
}
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
@ -229,10 +231,12 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(occ); CPUClass *cc = CPU_CLASS(occ);
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, openrisc_cpu_realizefn, device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
&occ->parent_realize); &occ->parent_realize);
device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
&occ->parent_phases);
cc->class_by_name = openrisc_cpu_class_by_name; cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work; cc->has_work = openrisc_cpu_has_work;

4
target/openrisc/cpu.h
View file

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/** /**
* OpenRISCCPUClass: * OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* *
* A OpenRISC CPU model. * A OpenRISC CPU model.
*/ */
@ -44,7 +44,7 @@ struct OpenRISCCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
}; };
#define TARGET_INSN_START_EXTRA_WORDS 1 #define TARGET_INSN_START_EXTRA_WORDS 1