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hw/mem/cxl_type3: Add paired msix_uninit_exclusive_bar() call

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msix_uninit_exclusive_bar() should be paired with msix_init_exclusive_bar()

Ensure proper resource cleanup by adding the missing
`msix_uninit_exclusive_bar()` call for the Type3 CXL device.

Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20250203161908.145406-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Li Zhijian 2025-02-03 16:19:05 +00:00 • committed by Michael S. Tsirkin
parent 8f90a54cfa
commit 0401c4328f
1 changed files with 2 additions and 0 deletions
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2
hw/mem/cxl_type3.c
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@ -944,6 +944,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
err_release_cdat:
cxl_doe_cdat_release(cxl_cstate);
err_free_special_ops:
msix_uninit_exclusive_bar(pci_dev);
g_free(regs->special_ops);
err_address_space_free:
if (ct3d->dc.host_dc) {
@ -967,6 +968,7 @@ static void ct3_exit(PCIDevice *pci_dev)
pcie_aer_exit(pci_dev);
cxl_doe_cdat_release(cxl_cstate);
msix_uninit_exclusive_bar(pci_dev);
g_free(regs->special_ops);
if (ct3d->dc.host_dc) {
cxl_destroy_dc_regions(ct3d);