mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 08:43:55 -06:00
target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
96eda02412
commit
03fb8cfc63
6 changed files with 381 additions and 449 deletions
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@ -186,30 +186,6 @@ static TCGv_i64 gen_dest_fpr_D(void)
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return cpu_tmp64;
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
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{
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tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
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offsetof(CPU_DoubleU, l.upper));
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tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_load_fpr_DT1(unsigned int src)
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{
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tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +
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offsetof(CPU_DoubleU, l.upper));
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tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
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offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_store_DT0_fpr(unsigned int dst)
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{
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tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +
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offsetof(CPU_DoubleU, l.upper));
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tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_load_fpr_QT0(unsigned int src)
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{
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tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
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@ -1490,20 +1466,20 @@ static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
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}
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}
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static inline void gen_op_fcmpd(int fccno)
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static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
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{
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switch (fccno) {
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case 0:
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gen_helper_fcmpd(cpu_env);
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gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
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break;
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case 1:
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gen_helper_fcmpd_fcc1(cpu_env);
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gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
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break;
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case 2:
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gen_helper_fcmpd_fcc2(cpu_env);
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gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
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break;
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case 3:
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gen_helper_fcmpd_fcc3(cpu_env);
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gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
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break;
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}
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}
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@ -1544,20 +1520,20 @@ static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
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}
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}
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static inline void gen_op_fcmped(int fccno)
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static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
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{
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switch (fccno) {
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case 0:
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gen_helper_fcmped(cpu_env);
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gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
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break;
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case 1:
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gen_helper_fcmped_fcc1(cpu_env);
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gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
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break;
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case 2:
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gen_helper_fcmped_fcc2(cpu_env);
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gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
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break;
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case 3:
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gen_helper_fcmped_fcc3(cpu_env);
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gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
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break;
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}
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}
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@ -1587,9 +1563,9 @@ static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
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gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
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}
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static inline void gen_op_fcmpd(int fccno)
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static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
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{
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gen_helper_fcmpd(cpu_env);
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gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
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}
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static inline void gen_op_fcmpq(int fccno)
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@ -1602,9 +1578,9 @@ static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
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gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
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}
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static inline void gen_op_fcmped(int fccno)
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static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
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{
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gen_helper_fcmped(cpu_env);
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gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
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}
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static inline void gen_op_fcmpeq(int fccno)
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@ -2461,12 +2437,12 @@ static void disas_sparc_insn(DisasContext * dc)
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break;
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case 0x2a: /* fsqrtd */
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CHECK_FPU_FEATURE(dc, FSQRT);
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fsqrtd(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fsqrtd(cpu_dst_64, cpu_env, cpu_src1_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x2b: /* fsqrtq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2488,13 +2464,14 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0x42: /* faddd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_faddd(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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cpu_src2_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_faddd(cpu_dst_64, cpu_env,
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cpu_src1_64, cpu_src2_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x43: /* faddq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2517,13 +2494,14 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0x46: /* fsubd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fsubd(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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cpu_src2_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fsubd(cpu_dst_64, cpu_env,
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cpu_src1_64, cpu_src2_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x47: /* fsubq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2548,13 +2526,14 @@ static void disas_sparc_insn(DisasContext * dc)
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break;
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case 0x4a: /* fmuld */
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CHECK_FPU_FEATURE(dc, FMUL);
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fmuld(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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cpu_src2_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fmuld(cpu_dst_64, cpu_env,
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cpu_src1_64, cpu_src2_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x4b: /* fmulq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2578,13 +2557,14 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0x4e: /* fdivd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fdivd(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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cpu_src2_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fdivd(cpu_dst_64, cpu_env,
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cpu_src1_64, cpu_src2_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x4f: /* fdivq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2601,17 +2581,18 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_clear_float_exceptions();
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cpu_src1_32 = gen_load_fpr_F(dc, rs1);
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cpu_src2_32 = gen_load_fpr_F(dc, rs2);
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gen_helper_fsmuld(cpu_env, cpu_src1_32, cpu_src2_32);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fsmuld(cpu_dst_64, cpu_env,
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cpu_src1_32, cpu_src2_32);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x6e: /* fdmulq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fdmulq(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs1);
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cpu_src2_64 = gen_load_fpr_D(dc, rs2);
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gen_helper_fdmulq(cpu_env, cpu_src1_64, cpu_src2_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_QT0_fpr(QFPREG(rd));
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gen_update_fprs_dirty(QFPREG(rd));
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@ -2625,10 +2606,10 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0xc6: /* fdtos */
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_32 = gen_dest_fpr_F();
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gen_helper_fdtos(cpu_dst_32, cpu_env);
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gen_helper_fdtos(cpu_dst_32, cpu_env, cpu_src1_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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@ -2643,24 +2624,24 @@ static void disas_sparc_insn(DisasContext * dc)
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break;
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case 0xc8: /* fitod */
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cpu_src1_32 = gen_load_fpr_F(dc, rs2);
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gen_helper_fitod(cpu_env, cpu_src1_32);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fitod(cpu_dst_64, cpu_env, cpu_src1_32);
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0xc9: /* fstod */
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cpu_src1_32 = gen_load_fpr_F(dc, rs2);
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gen_helper_fstod(cpu_env, cpu_src1_32);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fstod(cpu_dst_64, cpu_env, cpu_src1_32);
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0xcb: /* fqtod */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_op_load_fpr_QT1(QFPREG(rs2));
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gen_clear_float_exceptions();
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gen_helper_fqtod(cpu_env);
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gen_op_load_fpr_QT1(QFPREG(rs2));
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fqtod(cpu_dst_64, cpu_env);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0xcc: /* fitoq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2678,8 +2659,8 @@ static void disas_sparc_insn(DisasContext * dc)
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break;
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case 0xce: /* fdtoq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_helper_fdtoq(cpu_env);
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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gen_helper_fdtoq(cpu_env, cpu_src1_64);
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gen_op_store_QT0_fpr(QFPREG(rd));
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gen_update_fprs_dirty(QFPREG(rd));
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break;
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@ -2692,10 +2673,10 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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case 0xd2: /* fdtoi */
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_32 = gen_dest_fpr_F();
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gen_helper_fdtoi(cpu_dst_32, cpu_env);
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gen_helper_fdtoi(cpu_dst_32, cpu_env, cpu_src1_64);
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gen_helper_check_ieee_exceptions(cpu_env);
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gen_store_fpr_F(dc, rd, cpu_dst_32);
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break;
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@ -2726,10 +2707,10 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_update_fprs_dirty(QFPREG(rd));
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break;
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case 0x6: /* V9 fnegd */
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_helper_fnegd(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fnegd(cpu_dst_64, cpu_src1_64);
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0x7: /* V9 fnegq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2739,10 +2720,10 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_update_fprs_dirty(QFPREG(rd));
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break;
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case 0xa: /* V9 fabsd */
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_helper_fabsd(cpu_env);
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gen_op_store_DT0_fpr(DFPREG(rd));
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gen_update_fprs_dirty(DFPREG(rd));
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cpu_src1_64 = gen_load_fpr_D(dc, rs2);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fabsd(cpu_dst_64, cpu_env, cpu_src1_64);
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gen_store_fpr_D(dc, rd, cpu_dst_64);
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break;
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case 0xb: /* V9 fabsq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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@ -2754,49 +2735,49 @@ static void disas_sparc_insn(DisasContext * dc)
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case 0x81: /* V9 fstox */
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gen_clear_float_exceptions();
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cpu_src1_32 = gen_load_fpr_F(dc, rs2);
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gen_helper_fstox(cpu_env, cpu_src1_32);
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cpu_dst_64 = gen_dest_fpr_D();
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gen_helper_fstox(cpu_dst_64, cpu_env, cpu_src1_32);
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gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x82: /* V9 fdtox */
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_clear_float_exceptions();
|
||||
gen_helper_fdtox(cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fdtox(cpu_dst_64, cpu_env, cpu_src1_64);
|
||||
gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x83: /* V9 fqtox */
|
||||
CHECK_FPU_FEATURE(dc, FLOAT128);
|
||||
gen_op_load_fpr_QT1(QFPREG(rs2));
|
||||
gen_clear_float_exceptions();
|
||||
gen_helper_fqtox(cpu_env);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fqtox(cpu_dst_64, cpu_env);
|
||||
gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x84: /* V9 fxtos */
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_clear_float_exceptions();
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_32 = gen_dest_fpr_F();
|
||||
gen_helper_fxtos(cpu_dst_32, cpu_env);
|
||||
gen_helper_fxtos(cpu_dst_32, cpu_env, cpu_src1_64);
|
||||
gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_store_fpr_F(dc, rd, cpu_dst_32);
|
||||
break;
|
||||
case 0x88: /* V9 fxtod */
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_clear_float_exceptions();
|
||||
gen_helper_fxtod(cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fxtod(cpu_dst_64, cpu_env, cpu_src1_64);
|
||||
gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x8c: /* V9 fxtoq */
|
||||
CHECK_FPU_FEATURE(dc, FLOAT128);
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_clear_float_exceptions();
|
||||
gen_helper_fxtoq(cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fxtoq(cpu_env, cpu_src1_64);
|
||||
gen_helper_check_ieee_exceptions(cpu_env);
|
||||
gen_op_store_QT0_fpr(QFPREG(rd));
|
||||
gen_update_fprs_dirty(QFPREG(rd));
|
||||
|
@ -3046,9 +3027,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
|
||||
break;
|
||||
case 0x52: /* fcmpd, V9 %fcc */
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_op_fcmpd(rd & 3);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
|
||||
break;
|
||||
case 0x53: /* fcmpq, V9 %fcc */
|
||||
CHECK_FPU_FEATURE(dc, FLOAT128);
|
||||
|
@ -3062,9 +3043,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
|
||||
break;
|
||||
case 0x56: /* fcmped, V9 %fcc */
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_op_fcmped(rd & 3);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
|
||||
break;
|
||||
case 0x57: /* fcmpeq, V9 %fcc */
|
||||
CHECK_FPU_FEATURE(dc, FLOAT128);
|
||||
|
@ -3953,115 +3934,130 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
goto illegal_insn;
|
||||
case 0x020: /* VIS I fcmple16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmple16(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmple16(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x022: /* VIS I fcmpne16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpne16(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpne16(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x024: /* VIS I fcmple32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmple32(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmple32(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x026: /* VIS I fcmpne32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpne32(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpne32(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x028: /* VIS I fcmpgt16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpgt16(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpgt16(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x02a: /* VIS I fcmpeq16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpeq16(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpeq16(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x02c: /* VIS I fcmpgt32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpgt32(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpgt32(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x02e: /* VIS I fcmpeq32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fcmpeq32(cpu_dst, cpu_env);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
gen_helper_fcmpeq32(cpu_dst, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_movl_TN_reg(rd, cpu_dst);
|
||||
break;
|
||||
case 0x031: /* VIS I fmul8x16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmul8x16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmul8x16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x033: /* VIS I fmul8x16au */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmul8x16au(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmul8x16au(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x035: /* VIS I fmul8x16al */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmul8x16al(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmul8x16al(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x036: /* VIS I fmul8sux16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmul8sux16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmul8sux16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x037: /* VIS I fmul8ulx16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmul8ulx16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmul8ulx16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x038: /* VIS I fmuld8sux16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmuld8sux16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmuld8sux16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x039: /* VIS I fmuld8ulx16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fmuld8ulx16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fmuld8ulx16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x03a: /* VIS I fpack32 */
|
||||
case 0x03b: /* VIS I fpack16 */
|
||||
|
@ -4071,38 +4067,42 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
goto illegal_insn;
|
||||
case 0x048: /* VIS I faligndata */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_faligndata(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_faligndata(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x04b: /* VIS I fpmerge */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fpmerge(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fpmerge(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x04c: /* VIS II bshuffle */
|
||||
// XXX
|
||||
goto illegal_insn;
|
||||
case 0x04d: /* VIS I fexpand */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fexpand(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fexpand(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x050: /* VIS I fpadd16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fpadd16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fpadd16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x051: /* VIS I fpadd16s */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
|
@ -4115,11 +4115,12 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
case 0x052: /* VIS I fpadd32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fpadd32(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fpadd32(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x053: /* VIS I fpadd32s */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
|
@ -4131,11 +4132,12 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
case 0x054: /* VIS I fpsub16 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fpsub16(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fpsub16(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x055: /* VIS I fpsub16s */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
|
@ -4148,11 +4150,12 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
break;
|
||||
case 0x056: /* VIS I fpsub32 */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
gen_op_load_fpr_DT0(DFPREG(rs1));
|
||||
gen_op_load_fpr_DT1(DFPREG(rs2));
|
||||
gen_helper_fpsub32(cpu_env);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
|
||||
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
gen_helper_fpsub32(cpu_dst_64, cpu_env,
|
||||
cpu_src1_64, cpu_src2_64);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
case 0x057: /* VIS I fpsub32s */
|
||||
CHECK_FPU_FEATURE(dc, VIS1);
|
||||
|
@ -4811,16 +4814,10 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
}
|
||||
break;
|
||||
case 0x23: /* lddf, load double fpreg */
|
||||
{
|
||||
TCGv_i32 r_const;
|
||||
|
||||
r_const = tcg_const_i32(dc->mem_idx);
|
||||
gen_address_mask(dc, cpu_addr);
|
||||
gen_helper_lddf(cpu_addr, r_const);
|
||||
tcg_temp_free_i32(r_const);
|
||||
gen_op_store_DT0_fpr(DFPREG(rd));
|
||||
gen_update_fprs_dirty(DFPREG(rd));
|
||||
}
|
||||
gen_address_mask(dc, cpu_addr);
|
||||
cpu_dst_64 = gen_dest_fpr_D();
|
||||
tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
|
||||
gen_store_fpr_D(dc, rd, cpu_dst_64);
|
||||
break;
|
||||
default:
|
||||
goto illegal_insn;
|
||||
|
@ -4971,15 +4968,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
#endif
|
||||
#endif
|
||||
case 0x27: /* stdf, store double fpreg */
|
||||
{
|
||||
TCGv_i32 r_const;
|
||||
|
||||
gen_op_load_fpr_DT0(DFPREG(rd));
|
||||
r_const = tcg_const_i32(dc->mem_idx);
|
||||
gen_address_mask(dc, cpu_addr);
|
||||
gen_helper_stdf(cpu_addr, r_const);
|
||||
tcg_temp_free_i32(r_const);
|
||||
}
|
||||
gen_address_mask(dc, cpu_addr);
|
||||
cpu_src1_64 = gen_load_fpr_D(dc, rd);
|
||||
tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
|
||||
break;
|
||||
default:
|
||||
goto illegal_insn;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue