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tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE} target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} target/s390x: Improve general case of disas_jcc -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmXBpTAdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p6gf9HAasTSRECk2cvjW9 /mcJy0AIaespnI50fG8fm48OoFl0847CdrsJycpZ1spw3W3Wb0cVbMbq/teNMjXZ 0SGQJFk9Baq7wMhW7VzhSzJ96pcorpQprp7XBMdheLXqpT4zsM/EuwEAepBk8RUG 3kCeo38dswXE681ZafZkd/8pPzII19sQK8eiMpceeYkBsbbep+DDcnE18Ee4kISS u0SbuslKVahxd86LKuzrcz0pNFcmFuR5jRP9hmbQ0MfeAn0Pxlndi+ayZNghfgPf 3hDjskiionFwxb/OoRj45BssTWfDiluWl7IUsHfegPXCQ2Y+woT5Vq6TVGZn0GqS c6RLQQ== =TMiE -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging tcg: Introduce TCG_COND_TST{EQ,NE} target/alpha: Use TCG_COND_TST{EQ,NE} target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} target/s390x: Improve general case of disas_jcc # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmXBpTAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p6gf9HAasTSRECk2cvjW9 # /mcJy0AIaespnI50fG8fm48OoFl0847CdrsJycpZ1spw3W3Wb0cVbMbq/teNMjXZ # 0SGQJFk9Baq7wMhW7VzhSzJ96pcorpQprp7XBMdheLXqpT4zsM/EuwEAepBk8RUG # 3kCeo38dswXE681ZafZkd/8pPzII19sQK8eiMpceeYkBsbbep+DDcnE18Ee4kISS # u0SbuslKVahxd86LKuzrcz0pNFcmFuR5jRP9hmbQ0MfeAn0Pxlndi+ayZNghfgPf # 3hDjskiionFwxb/OoRj45BssTWfDiluWl7IUsHfegPXCQ2Y+woT5Vq6TVGZn0GqS # c6RLQQ== # =TMiE # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 Feb 2024 03:19:12 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits) tcg/tci: Support TCG_COND_TST{EQ,NE} tcg/s390x: Support TCG_COND_TST{EQ,NE} tcg/s390x: Add TCG_CT_CONST_CMP tcg/s390x: Split constraint A into J+U tcg/ppc: Support TCG_COND_TST{EQ,NE} tcg/ppc: Add TCG_CT_CONST_CMP tcg/ppc: Tidy up tcg_target_const_match tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc tcg/sparc64: Support TCG_COND_TST{EQ,NE} tcg/sparc64: Pass TCGCond to tcg_out_cmp tcg/sparc64: Hoist read of tcg_cond_to_rcond tcg/i386: Use TEST r,r to test 8/16/32 bits tcg/i386: Improve TSTNE/TESTEQ vs powers of two tcg/i386: Support TCG_COND_TST{EQ,NE} tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp tcg/i386: Pass x86 condition codes to tcg_out_cmov tcg/arm: Support TCG_COND_TST{EQ,NE} tcg/arm: Split out tcg_out_cmp() tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
03e4bc0bc0
38 changed files with 1379 additions and 595 deletions
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@ -754,10 +754,10 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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case CC_OP_TM_64:
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switch (mask) {
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case 8:
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cond = TCG_COND_EQ;
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cond = TCG_COND_TSTEQ;
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break;
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case 4 | 2 | 1:
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cond = TCG_COND_NE;
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cond = TCG_COND_TSTNE;
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break;
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default:
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goto do_dynamic;
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@ -768,11 +768,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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case CC_OP_ICM:
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switch (mask) {
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case 8:
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cond = TCG_COND_EQ;
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cond = TCG_COND_TSTEQ;
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break;
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case 4 | 2 | 1:
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case 4 | 2:
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cond = TCG_COND_NE;
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cond = TCG_COND_TSTNE;
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break;
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default:
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goto do_dynamic;
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@ -854,18 +854,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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c->u.s64.a = cc_dst;
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c->u.s64.b = tcg_constant_i64(0);
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break;
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case CC_OP_LTGT_64:
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case CC_OP_LTUGTU_64:
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c->u.s64.a = cc_src;
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c->u.s64.b = cc_dst;
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break;
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case CC_OP_TM_32:
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case CC_OP_TM_64:
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case CC_OP_ICM:
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c->u.s64.a = tcg_temp_new_i64();
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c->u.s64.b = tcg_constant_i64(0);
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tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
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c->u.s64.a = cc_src;
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c->u.s64.b = cc_dst;
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break;
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case CC_OP_ADDU:
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@ -889,67 +885,45 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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case CC_OP_STATIC:
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c->is_64 = false;
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c->u.s32.a = cc_op;
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switch (mask) {
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case 0x8 | 0x4 | 0x2: /* cc != 3 */
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cond = TCG_COND_NE;
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/* Fold half of the cases using bit 3 to invert. */
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switch (mask & 8 ? mask ^ 0xf : mask) {
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case 0x1: /* cc == 3 */
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cond = TCG_COND_EQ;
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c->u.s32.b = tcg_constant_i32(3);
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break;
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case 0x8 | 0x4 | 0x1: /* cc != 2 */
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cond = TCG_COND_NE;
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c->u.s32.b = tcg_constant_i32(2);
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break;
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case 0x8 | 0x2 | 0x1: /* cc != 1 */
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cond = TCG_COND_NE;
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
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cond = TCG_COND_EQ;
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c->u.s32.a = tcg_temp_new_i32();
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c->u.s32.b = tcg_constant_i32(0);
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tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
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break;
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case 0x8 | 0x4: /* cc < 2 */
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cond = TCG_COND_LTU;
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c->u.s32.b = tcg_constant_i32(2);
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break;
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case 0x8: /* cc == 0 */
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cond = TCG_COND_EQ;
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c->u.s32.b = tcg_constant_i32(0);
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break;
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case 0x4 | 0x2 | 0x1: /* cc != 0 */
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cond = TCG_COND_NE;
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c->u.s32.b = tcg_constant_i32(0);
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break;
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case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
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cond = TCG_COND_NE;
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c->u.s32.a = tcg_temp_new_i32();
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c->u.s32.b = tcg_constant_i32(0);
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tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
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break;
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case 0x4: /* cc == 1 */
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cond = TCG_COND_EQ;
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x2 | 0x1: /* cc > 1 */
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cond = TCG_COND_GTU;
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x2: /* cc == 2 */
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cond = TCG_COND_EQ;
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c->u.s32.b = tcg_constant_i32(2);
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break;
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case 0x1: /* cc == 3 */
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case 0x4: /* cc == 1 */
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cond = TCG_COND_EQ;
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c->u.s32.b = tcg_constant_i32(3);
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x2 | 0x1: /* cc == 2 || cc == 3 => cc > 1 */
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cond = TCG_COND_GTU;
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
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cond = TCG_COND_TSTNE;
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c->u.s32.b = tcg_constant_i32(1);
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break;
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case 0x4 | 0x2: /* cc == 1 || cc == 2 => (cc - 1) <= 1 */
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cond = TCG_COND_LEU;
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c->u.s32.a = tcg_temp_new_i32();
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c->u.s32.b = tcg_constant_i32(1);
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tcg_gen_addi_i32(c->u.s32.a, cc_op, -1);
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break;
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case 0x4 | 0x2 | 0x1: /* cc != 0 */
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cond = TCG_COND_NE;
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c->u.s32.b = tcg_constant_i32(0);
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break;
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default:
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/* CC is masked by something else: (8 >> cc) & mask. */
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cond = TCG_COND_NE;
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c->u.s32.a = tcg_temp_new_i32();
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c->u.s32.b = tcg_constant_i32(0);
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tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
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tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
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break;
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/* case 0: never, handled above. */
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g_assert_not_reached();
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}
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if (mask & 8) {
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cond = tcg_invert_cond(cond);
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}
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break;
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