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target/mips: Implement Loongson CSR instructions

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Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.

Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.

Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY:  Fixed typo in ase_lcsr_available(),
      retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
      restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Jiaxun Yang 2023-05-21 19:01:46 +01:00 • committed by Philippe Mathieu-Daudé
parent b263688d23
commit 03afdc28b3
14 changed files with 238 additions and 0 deletions
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9
target/mips/cpu-defs.c.inc
View file

@ -895,6 +895,15 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
.lcsr_cpucfg1 = (1 << CPUCFG1_FP) | (2 << CPUCFG1_FPREV) |
(1 << CPUCFG1_MSA1) | (1 << CPUCFG1_LSLDR0) |
(1 << CPUCFG1_LSPERF) | (1 << CPUCFG1_LSPERFX) |
(1 << CPUCFG1_LSSYNCI) | (1 << CPUCFG1_LLEXC) |
(1 << CPUCFG1_SCRAND) | (1 << CPUCFG1_MUALP) |
(1 << CPUCFG1_KMUALEN) | (1 << CPUCFG1_ITLBT) |
(1 << CPUCFG1_SFBP) | (1 << CPUCFG1_CDMAP),
.lcsr_cpucfg2 = (1 << CPUCFG2_LEXT1) | (1 << CPUCFG2_LCSRP) |
(1 << CPUCFG2_LDISBLIKELY),
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |