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target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c

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Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based
upon xA and xB at translation time.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20190616123751.781-9-mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland 2019-06-16 13:37:44 +01:00 • committed by David Gibson
parent 75cf84cbee
commit 033e1fcd97
3 changed files with 36 additions and 21 deletions
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15
target/ppc/fpu_helper.c
View file

@ -2179,10 +2179,9 @@ VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
* nbits - number of fraction bits
*/
#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
void helper_##op(CPUPPCState *env, uint32_t opcode, \
ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t *xa = &env->vsr[xA(opcode)]; \
ppc_vsr_t *xb = &env->vsr[xB(opcode)]; \
int i; \
int fe_flag = 0; \
int fg_flag = 0; \
@ -2431,10 +2430,9 @@ VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode)
void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t *xa, ppc_vsr_t *xb)
{
ppc_vsr_t *xa = &env->vsr[xA(opcode)];
ppc_vsr_t *xb = &env->vsr[xB(opcode)];
int64_t exp_a, exp_b;
uint32_t cc;
@ -2492,10 +2490,9 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
}
#define VSX_SCALAR_CMP(op, ordered) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
void helper_##op(CPUPPCState *env, uint32_t opcode, \
ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t *xa = &env->vsr[xA(opcode)]; \
ppc_vsr_t *xb = &env->vsr[xB(opcode)]; \
uint32_t cc = 0; \
bool vxsnan_flag = false, vxvc_flag = false; \
\