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target/arm: Refactor handling of timer offset for direct register accesses
When reading or writing the timer registers, sometimes we need to apply one of the timer offsets. Specifically, this happens for direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It also applies for direct reads and writes of the CNT*_TVAL_EL* registers that provide the 32-bit downcounting view of each timer. We currently do this with duplicated code in gt_tval_read() and gt_tval_write() and a special-case in gt_virt_cnt_read() and gt_cnt_read(). Refactor this so that we handle it all in a single function gt_direct_access_timer_offset(), to parallel how we handle the offset for indirect accesses. The call in the WFIT helper previously to gt_virt_cnt_offset() is now to gt_direct_access_timer_offset(); this is the correct behaviour, but it's not immediately obvious that it shouldn't be considered an indirect access, so we add an explanatory comment. This commit should make no behavioural changes. (Cc to stable because the following bugfix commit will depend on this one.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org
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3 changed files with 62 additions and 54 deletions
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@ -1819,9 +1819,10 @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
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uint64_t gt_get_countervalue(CPUARMState *env);
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/*
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* Return the currently applicable offset between the system counter
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* and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
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* and the counter for the specified timer, as used for direct register
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* accesses.
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*/
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uint64_t gt_virt_cnt_offset(CPUARMState *env);
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uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx);
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/*
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* Return mask of ARMMMUIdxBit values corresponding to an "invalidate
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