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target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree

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Convert the following opcodes to decodetree:

- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-8-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-12 20:08:32 +01:00 • committed by Philippe Mathieu-Daudé
parent c112a5ddaa
commit 020cafa58e
4 changed files with 121 additions and 82 deletions
Download patch file Download diff file Expand all files Collapse all files

5
target/mips/tcg/godson2.decode
View file

@ -17,3 +17,8 @@ DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
MOD_G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd
MODU_G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd
DMOD_G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd
DMODU_G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd

5
target/mips/tcg/loong-ext.decode
View file

@ -18,3 +18,8 @@ DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
MOD_G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd
DMOD_G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd
MODU_G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd
DMODU_G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd

111
target/mips/tcg/loong_translate.c
View file

@ -141,6 +141,117 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIVU_G(s, a->rd, a->rs, a->rt, true); return gen_lext_DIVU_G(s, a->rd, a->rs, a->rt, true);
} }
static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
bool is_double)
{
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
l1 = gen_new_label();
l2 = gen_new_label();
l3 = gen_new_label();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
if (!is_double) {
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
}
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
if (!is_double) {
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
gen_set_label(l3);
return true;
}
static bool trans_MOD_G(DisasContext *s, arg_muldiv *a)
{
return gen_lext_MOD_G(s, a->rd, a->rs, a->rt, false);
}
static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)
{
return gen_lext_MOD_G(s, a->rd, a->rs, a->rt, true);
}
static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
bool is_double)
{
TCGv t0, t1;
TCGLabel *l1, *l2;
if (is_double) {
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
}
if (rd == 0) {
/* Treat as NOP. */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
l1 = gen_new_label();
l2 = gen_new_label();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
if (!is_double) {
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
}
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
if (!is_double) {
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
gen_set_label(l2);
return true;
}
static bool trans_MODU_G(DisasContext *s, arg_muldiv *a)
{
return gen_lext_MODU_G(s, a->rd, a->rs, a->rt, false);
}
static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
{
return gen_lext_MODU_G(s, a->rd, a->rs, a->rt, true);
}
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn) bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
{ {
if (!decode_64bit_enabled(ctx)) { if (!decode_64bit_enabled(ctx)) {

82
target/mips/tcg/translate.c
View file

@ -332,10 +332,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
/* Misc */ /* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2, OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2, OPC_CLO = 0x21 | OPC_SPECIAL2,
@ -369,10 +365,6 @@ enum {
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
/* MIPS DSP Load */ /* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3, OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
@ -3607,42 +3599,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break; break;
case OPC_MOD_G_2E:
case OPC_MOD_G_2F:
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGLabel *l3 = gen_new_label();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
gen_set_label(l3);
}
break;
case OPC_MODU_G_2E:
case OPC_MODU_G_2F:
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
gen_set_label(l2);
}
break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E: case OPC_DMULT_G_2E:
case OPC_DMULT_G_2F: case OPC_DMULT_G_2F:
@ -3652,36 +3608,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F: case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break; break;
case OPC_DMOD_G_2E:
case OPC_DMOD_G_2F:
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
gen_set_label(l3);
}
break;
case OPC_DMODU_G_2E:
case OPC_DMODU_G_2F:
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
gen_set_label(l2);
}
break;
#endif #endif
} }
} }
@ -13543,8 +13469,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break; break;
case OPC_MULT_G_2F: case OPC_MULT_G_2F:
case OPC_MULTU_G_2F: case OPC_MULTU_G_2F:
case OPC_MOD_G_2F:
case OPC_MODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt); gen_loongson_integer(ctx, op1, rd, rs, rt);
break; break;
@ -13574,8 +13498,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break; break;
case OPC_DMULT_G_2F: case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F: case OPC_DMULTU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt); gen_loongson_integer(ctx, op1, rd, rs, rt);
break; break;
@ -13711,8 +13633,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode); op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULT_G_2E:
case OPC_MULTU_G_2E: case OPC_MULTU_G_2E:
/* /*
@ -13979,8 +13899,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E: case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E: case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E:
case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E); check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt); gen_loongson_integer(ctx, op1, rd, rs, rt);
break; break;