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trivial patches for 2014-09-03

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Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-09-03' into staging

trivial patches for 2014-09-03

# gpg: Signature made Wed 03 Sep 2014 06:53:42 BST using RSA key ID A4C3D7DB
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: 6F67 E18E 7C91 C5B1 5514  66A7 BEE5 9D74 A4C3 D7DB

* remotes/mjt/tags/trivial-patches-2014-09-03:
  slirp: Honour vlan/stack in hostfwd_remove commands
  hmp: fix MemdevList memory leak
  qom/object.c, hmp.c: fix string_output_get_string() memory leak
  query-memdev: fix potential memory leaks
  MAINTAINERS: Add VMWare devices maintainer
  device_tree.c: dump all err mesages with error_report
  device_tree.c: redirect load_device_tree err message to stderr
  scripts: Remove scripts/qtest
  Fix debug print warning
  curl: The macro that you have to uncomment to get debugging is DEBUG_CURL.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-09-04 13:33:53 +01:00
commit 01eb313907
14 changed files with 70 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

5
hw/i2c/pm_smbus.c
View file

@ -139,7 +139,8 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
{
PMSMBus *s = opaque;
SMBUS_DPRINTF("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
" val=0x%02" PRIx64 "\n", addr, val);
switch(addr) {
case SMBHSTSTS:
s->smb_stat = (~(val & 0xff)) & s->smb_stat;
@ -206,7 +207,7 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
val = 0;
break;
}
SMBUS_DPRINTF("SMB readb port=0x%04x val=0x%02x\n", addr, val);
SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", addr, val);
return val;
}

2
hw/i386/pc.c
View file

@ -481,7 +481,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
Port92State *s = opaque;
int oldval = s->outport;
DPRINTF("port92: write 0x%02x\n", val);
DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
s->outport = val;
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {

4
hw/input/pckbd.c
View file

@ -229,7 +229,7 @@ static void kbd_write_command(void *opaque, hwaddr addr,
{
KBDState *s = opaque;
DPRINTF("kbd: write cmd=0x%02x\n", val);
DPRINTF("kbd: write cmd=0x%02" PRIx64 "\n", val);
/* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
* low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
@ -330,7 +330,7 @@ static void kbd_write_data(void *opaque, hwaddr addr,
{
KBDState *s = opaque;
DPRINTF("kbd: write data=0x%02x\n", val);
DPRINTF("kbd: write data=0x%02" PRIx64 "\n", val);
switch(s->write_cmd) {
case 0:

2
hw/intc/i8259.c
View file

@ -370,7 +370,7 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
ret = s->imr;
}
}
DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
DPRINTF("read: addr=0x%02" HWADDR_PRIx " val=0x%02x\n", addr, ret);
return ret;
}

5
hw/isa/apm.c
View file

@ -41,7 +41,8 @@ static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
{
APMState *apm = opaque;
addr &= 1;
APM_DPRINTF("apm_ioport_writeb addr=0x%x val=0x%02x\n", addr, val);
APM_DPRINTF("apm_ioport_writeb addr=0x%" HWADDR_PRIx
" val=0x%02" PRIx64 "\n", addr, val);
if (addr == 0) {
apm->apmc = val;
@ -64,7 +65,7 @@ static uint64_t apm_ioport_readb(void *opaque, hwaddr addr, unsigned size)
} else {
val = apm->apms;
}
APM_DPRINTF("apm_ioport_readb addr=0x%x val=0x%02x\n", addr, val);
APM_DPRINTF("apm_ioport_readb addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, val);
return val;
}

2
hw/timer/mc146818rtc.c
View file

@ -391,7 +391,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
if ((addr & 1) == 0) {
s->cmos_index = data & 0x7f;
} else {
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
s->cmos_index, data);
switch(s->cmos_index) {
case RTC_SECONDS_ALARM: