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ppc/xive2: Change context/ring specific functions to be generic

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Some the functions that have been created are specific to a ring or context. Some
of these same functions are being changed to operate on any ring/context. This  will
simplify the next patch sets that are adding additional ring/context operations.

Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Michael Kowal 2024-09-13 11:16:54 -05:00 • committed by Nicholas Piggin
parent f82fec6c1f
commit 00a7a7a548
3 changed files with 14 additions and 14 deletions
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6
hw/intc/xive.c
View file

@ -114,7 +114,7 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
} }
} }
void xive_tctx_reset_os_signal(XiveTCTX *tctx) void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring)
{ {
/* /*
* Lower the External interrupt. Used when pulling an OS * Lower the External interrupt. Used when pulling an OS
@ -122,7 +122,7 @@ void xive_tctx_reset_os_signal(XiveTCTX *tctx)
* context. It should be raised again when re-pushing the OS * context. It should be raised again when re-pushing the OS
* context. * context.
*/ */
qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS)); qemu_irq_lower(xive_tctx_output(tctx, ring));
} }
static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
@ -424,7 +424,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
xive_tctx_set_os_cam(tctx, qw1w2_new); xive_tctx_set_os_cam(tctx, qw1w2_new);
xive_tctx_reset_os_signal(tctx); xive_tctx_reset_signal(tctx, TM_QW1_OS);
return qw1w2; return qw1w2;
} }

18
hw/intc/xive2.c
View file

@ -270,13 +270,14 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)
* the NVP by changing the H bit while the context is enabled * the NVP by changing the H bit while the context is enabled
*/ */
static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
uint8_t nvp_blk, uint32_t nvp_idx) uint8_t nvp_blk, uint32_t nvp_idx,
uint8_t ring)
{ {
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value; uint32_t pir = env->spr_cb[SPR_PIR].default_value;
Xive2Nvp nvp; Xive2Nvp nvp;
uint8_t *regs = &tctx->regs[TM_QW1_OS]; uint8_t *regs = &tctx->regs[ring];
if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
@ -321,7 +322,7 @@ static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
} }
static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk,
uint32_t *nvp_idx, bool *vo, bool *ho) uint32_t *nvp_idx, bool *vo, bool *ho)
{ {
*nvp_blk = xive2_nvp_blk(cam); *nvp_blk = xive2_nvp_blk(cam);
@ -330,7 +331,6 @@ static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
*ho = !!(cam & TM2_QW1W2_HO); *ho = !!(cam & TM2_QW1W2_HO);
} }
/* /*
* Encode the HW CAM line with 7bit or 8bit thread id. The thread id * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
* width and block id width is configurable at the IC level. * width and block id width is configurable at the IC level.
@ -363,7 +363,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
bool vo; bool vo;
bool do_save; bool do_save;
xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);
if (!vo) { if (!vo) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
@ -375,10 +375,10 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx); xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, TM_QW1_OS);
} }
xive_tctx_reset_os_signal(tctx); xive_tctx_reset_signal(tctx, TM_QW1_OS);
return qw1w2; return qw1w2;
} }
@ -573,7 +573,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
bool vo; bool vo;
bool do_restore; bool do_restore;
xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
/* First update the thead context */ /* First update the thead context */
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);

2
include/hw/ppc/xive.h
View file

@ -533,7 +533,7 @@ Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx);
void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
void xive_tctx_reset_os_signal(XiveTCTX *tctx); void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
/* /*
* KVM XIVE device helpers * KVM XIVE device helpers